Method for encapsulating a multi-chip substrate array

Abstract

An encapsulation method enabling high throughput production of semiconductor die packages. In an exemplary embodiment, a mold is provided with an upper mold platen having a plurality of cavities for encapsulating interconnections on a first side of a multi-chip carrier substrate. The mold further includes a lower mold platen having a cavity for encapsulating substantially the entire second side of the carrier substrate, including a plurality IC chips mounted thereon. Substrate support elements, in the form of standoff pins, are provided for supporting the carrier substrate during the encapsulation process to prevent substrate deflection. The standoff pins may be integral to a mold cavity or may be removable. The standoff pins may further be aligned along lines representing individual device package edges. Cutting along marks left in the encapsulant by the support elements provides individual device packages.

Dependencies are inferred from the claim text.