US 6,746,893 B1 · Transistor with variable electron affinity gate and methods of fabrication and use

Abstract

A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Claims45

Dependent claims

A method of fabricating a transistor in a semiconductor substrate, the method comprising:

forming a source region and a drain region in a semiconductor substrate, a channel region being between the source region and the drain region;
forming an insulating layer on the channel region;
forming a floating gate on the insulating layer, wherein the floating gate comprises a silicon carbide compound Si1−xCx;
selecting x to be between 0 and 1.0;
forming an intergate dielectric over the floating gate;
and
forming a polysilicon control gate over the intergate dielectric.

4 more elements

A method of fabricating a transistor comprising:

forming a source region and a drain region in a substrate that are separated by a channel region in the substrate;
forming an insulating layer on the substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a gate on the substrate;
forming an intergate dielectric on the gate;
and
forming a polysilicon control gate over the intergate dielectric.

4 more elements

A method of fabricating a transistor comprising:

forming a source region and a drain region in a silicon substrate that are separated by a channel region in the silicon substrate;
forming an insulating layer on the silicon substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
doping the layer of the silicon carbide compound Si1−xCx with a p-type implantation;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a gate on the silicon substrate;
forming an intergate dielectric on the gate;
and
forming a polysilicon control gate over the intergate dielectric.

5 more elements

A method of fabricating a transistor comprising:

forming a source region and a drain region in a silicon substrate that are separated by a channel region in the silicon substrate;
forming an insulating layer on the silicon substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
doping the layer of the silicon carbide compound Si1−xCx with an n-type ion implantation;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a gate on the silicon substrate;
forming an intergate dielectric on the gate;
and
forming a polysilicon control gate over the intergate dielectric.

5 more elements

A method of fabricating a floating gate transistor comprising:

forming a source region and a drain region in a substrate that are separated by a channel region in the substrate;
forming an insulating layer on the substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a floating gate on the substrate;
forming an intergate dielectric on the floating gate;
and
forming a polysilicon control gate over the intergate dielectric.

4 more elements

A method of fabricating a floating gate transistor comprising:

forming a source region and a drain region in a silicon substrate that are separated by a channel region in the silicon substrate;
forming an insulating layer on the silicon substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
doping the layer of the silicon carbide compound Si1−xCx with an n-type ion implantation;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a floating gate on the silicon substrate;
forming an intergate dielectric on the floating gate;
and
forming a polysilicon control gate over the intergate dielectric.

5 more elements

A method of fabricating a memory cell comprising:

forming a source region and a drain region in a substrate that are separated by a channel region in the substrate;
forming an insulating layer on the substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a floating gate on the substrate;
forming an intergate dielectric on the floating gate;
and
forming a polysilicon control gate over the intergate dielectric that is coupled to receive a control voltage from a memory device.

4 more elements

A method of fabricating a memory cell comprising:

forming a source region and a drain region in a silicon substrate that are separated by a channel region in the silicon substrate;
forming an insulating layer on the silicon substrate;
forming a layer of a silicon carbide compound Si1−xCx on the insulating layer wherein x is between 0 and 1.0;
doping the layer of the silicon carbide compound Si1−xCx with an n-type ion implantation;
removing portions of the insulating layer and the layer of the silicon carbide compound Si1−xCx to form a floating gate on the silicon substrate;
forming an intergate dielectric on the floating gate;
and
forming a polysilicon control gate over the intergate dielectric that is coupled to receive a control voltage from a memory device.

5 more elements

Dependencies are inferred from the claim text.

Transistor with variable electron affinity gate and methods of fabrication and use

Life of this patent

Transistor with variable electron affinity gate and methods of fabrication and use

Life of this patent

Abstract

Claims45