Method for phase locking in a phase lock loop
AssigneeCypress Semiconductor Corporation
InventorsNathan Y. Moyal, Mark R. Gehring, Russell Moen, Lawrence Ragan
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Abstract
An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.
Claims21
An apparatus comprising:
- a phase lock loop (PLL) configured to multiply an input frequency to generate an output frequency in response to a multi-bit lock signal;
- and
- a lock circuit configured to generate said multi-bit lock signal, wherein said PLL is configured to (i) (a) select a reference frequency as said input frequency and (b) select a first feedback ratio, when in a first mode and (ii) (a) select one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) select a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.
An apparatus comprising:
- means for multiplying an input frequency in response to a lock signal;
- means for generating an output frequency in response to said input frequency;
- means for generating said lock signal;
- and
- means for (i) (a) selecting a reference frequency to be said input frequency and (b) selecting a first feedback ratio, when in a first mode and (ii) (a) selecting one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) selecting a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.
A method for frequency and/or phase acquisition in a phase lock loop (PLL), comprising the steps of:
- (A) multiplying an input frequency in response to a lock signal;
- (B) generating said lock signal;
- and
- (C) (i) (a) selecting said reference frequency to be said input frequency and (b) selecting a first feedback ratio, when in a first mode and (ii) (a) selecting one of a plurality of divided frequencies of said reference frequency to be said input frequency and (b) selecting a second feedback ratio, when in a second mode, wherein (i) said selected divided frequency is selected in response to said multi-bit lock signal, (ii) a first bit of said multi-bit lock signal selects said first feedback ratio, and (iii) a second bit of said multi-bit lock signal selects said second feedback ratio.
An apparatus comprising:
- a phase lock loop (PLL) configured to multiply an input frequency to generate an output frequency in response to a lock signal;
- and
- a lock circuit configured to generate said lock signal in response to an external input derived independently from said PLL, wherein said PLL is configured to (i) select a reference frequency as said input frequency when in a first mode and (ii) select a divided frequency of said reference frequency as said input frequency when in a second mode, wherein either said first mode or said second mode is selected in response to said lock signal.
Dependencies are inferred from the claim text.