Dual-port buffer-to-memory interface

A memory module comprising:

• R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
• a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;
• an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×m-bit-wide data transfers with the R ranks of memory devices, the interface circuit comprising
• R m-bit-wide data registers, each register capable of exchanging point-to-point data signaling with a corresponding rank of memory devices through the data port of that rank, and
• a multiplexer, having a multiplexing ratio R, coupled between the R data registers and the external data port;
• and
• a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×m-bit-wide data transfer with the memory device ranks.

A memory module comprising:

• R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
• a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;
• an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×m-bit-wide data transfers with the R ranks of memory devices;
• and
• a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×m-bit-wide data transfer with the memory device ranks;
• wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, wherein each port is capable of connection to an m-bit-wide memory data bus segment, wherein one port comprises a transfer port and the other port comprises a forwarding port, the module capable of using the transfer port to transfer data signals between the interface circuit and a higher-level controller connected to the memory data bus, the module capable of using the forwarding port to connect to a second memory module in order to transfer data signals between the transfer port on the first memory module and the transfer port on the second memory module.

A memory module comprising:

• R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
• a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;
• an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×m-bit-wide data transfers with the R ranks of memory devices;
• and
• a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×m-bit-wide data transfer with the memory device ranks,
• wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, wherein each module data port is capable of connection to an m/2-bit-wide memory data bus segment, wherein the dual module data ports comprise first and second transfer/forwarding ports, the module capable of retransmitting data signals received at one of the transfer/forwarding ports, but not destined for that memory module, on the other transfer/forwarding port, the module also capable of transferring m/2 data signals between each of the transfer/forwarding ports and the interface circuit.

A method of host/memory communication comprising:

• initiating a data access transaction, involving N data bits, between a memory controller and a memory module;
• at the memory module, initiating a corresponding data access transaction between an interface circuit and R ranks of memory devices, each rank capable of m-bit-wide data transfers, R>1;
• transferring the N data bits between the memory controller and the memory module in m-bit-wide data segments;
• and
• transferring the N data bits between the interface circuit and the R ranks of memory devices in M R×m-bit-wide segments, where M = N R × m
• is an integer value,
• wherein the method further comprises initiating a valid data access transaction when N is an integer multiple of m, but less than R×m.