SLM display data address mapping for four bank frame buffer
AssigneeTexas Instruments Incorporated
InventorsJeffrey S. Farris, Alan Hearn
Life of this patent
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Abstract
A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.
Claims9
A method of addressing double buffered memory for an SLM, the memory address having only two bank bits, the method comprising the steps of:
- mapping a bit plane bit to a first bank bit;
- mapping a pixel position bit to a second bank bit;
- mapping a read/write bit to a column address bit;
- and
- mapping the remaining bit plane and pixel position bits to row address and column address bits.
Dependencies are inferred from the claim text.