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US 6,741,130 B2Granted
High-speed output transconductance amplifier capable of operating at different voltage levels
OwnerMeng-Jer Wey, Jeng-Huang Wuinventors
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Abstract
A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels. The high-speed output transconductance amplifier configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at lower voltage and normal voltage, for example, a receiver can be operated in both for SSTL-3 (3.3V system) and SSTL-2 (2.5V system).
Claims8
A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels, comprising:
- an NMOS current mirror circuit consisting of a first NMOS with a drain and a gate, and a diode-configured NMOS with a drain and a gate connected to the gate of the first NMOS and the drain of the diode-configured NMOS;
- two PMOS current mirror circuits consisting of a first PMOS with a gate and a drain connected to the drain of the first NMOS to form a connection point as an output terminal, a second PMOS with a gate and a drain connected to the drain of the diode-configured NMOS, a first diode-configured PMOS with a drain and a gate connected the drain of the first diode-configured PMOS and the gate of the first PMOS, and a second diode-configured PMOS with a drain and a gate connected to the drain of the second diode-configured PMOS and the gate of the second PMOS;
- a cross-coupled circuit consisting of a first cross-coupled unit having a first programmable switch and a third PMOS connected in parallel to the first PMOS, with a gate connected to the first programmable switch, and a second cross-coupled unit having a second programmable switch and a fourth PMOS connected in parallel to the second diode-configured PMOS, with a gate connected to the second programmable switch;
- and
- a differential operational amplifier consisting of a second NMOS with a drain connected to the first switch and the drain of the second diode-configured PMOS, a gate connected to a first voltage, and a source, a third NMOS with a drain connected to the second switch and the drain of the first diode-configured PMOS, a gate connected to a second voltage, and a source, and a fourth NMOS with a drain connected to the sources of the second and third NMOSs and a gate connected to a third voltage, wherein the first NMOS, the fourth NMOS, and the first diode-configured NMOS respectively are grounded.
2 more elements
Dependencies are inferred from the claim text.