Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device

A semiconductor package for three-dimensional mounting, comprising:

• a first substrate having an upper surface on which a first metal pattern is formed and a lower surface on which a second metal pattern is formed, said first metal pattern and second metal pattern being electrically connected to each other;
• a semiconductor chip which is placed on the upper surface of the first substrate and is electrically connected to the first metal pattern;
• a sealing resin layer which is formed on the upper surface of the first substrate and seals the semiconductor chip and the first metal pattern;
• a conductive wire which passes through the resin layer and has one end electrically connected to the first metal pattern and the other end exposed at a top surface of the resin layer, the exposed other end of said conductive wire and the top surface of the resin layer being substantially level with each other;
• a first electrode which is formed on the lower surface of the first substrate and is electrically connected to the second metal pattern;
• a wiring pattern formed over the sealing resin layer and being electrically connected to the conductive wire, said wiring pattern being comprised of at least a first wiring and a second wiring, said first wiring being disposed closer to a center of the semiconductor package than said second wiring is, and said second wiring being disposed closer toward a periphery of the semiconductor package than said first wiring is,
• wherein said wiring pattern comprises a plurality of said first wirings, and a plurality of said second wirings, said first wirings and said second wirings being alternatingly arranged.

A semiconductor package for three-dimensional mounting, comprising:

• a first substrate having an upper surface on which a first metal pattern is formed and a lower surface on which a second metal pattern is formed, said first metal pattern and second metal pattern being electrically connected to each other;
• a semiconductor chip which is placed on the upper surface of the first substrate and is electrically connected to the first metal pattern;
• a sealing resin layer which is formed on the upper surface of the first substrate and seals the semiconductor chip and the first metal pattern;
• a conductive wire which passes through the resin layer and has one end electrically connected to the first metal pattern and the other end exposed at a top surface of the resin layer, the exposed other end of said conductive wire and the top surface of the resin layer being substantially level with each other;
• a first electrode which is formed on the lower surface of the first substrate and is electrically connected to the second metal pattern;
• a wiring pattern formed over the sealing resin layer and being electrically connected to the conductive wire, said wiring pattern being comprised of Cu;
• and
• a second electrode formed on the wiring pattern, the second electrode including an Ni layer in electrical connection with the wiring pattern, and an Au layer disposed on the Ni layer.