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US 6,735,682 B2Granted
Apparatus and method for address calculation
AssigneeIntel Corporation
InventorsRoss A. Segelken, Feng Chen, David J. Sager
Life of this patent
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Abstract
A dual-cycle address generation unit is described to generate linear addresses. The dual-cycle address generation unit includes a first adder to add a product of an index and a scaling factor to an offset and a segment base during a first clock cycle and a second adder to add output of the first adder with a base during a second clock cycle.
Claims21
An address generation unit comprising:
- a first adder to add a product of an index and a scaling factor to an offset and a segment base during a first clock cycle;
- and
- a second adder to add output of the first adder with a base during a second clock cycle.
A processor comprising:
- an execution core;
- a register file;
- a scheduler coupled to said execution core and said register file;
- and
- an address generation unit (AGU) coupled to said scheduler to generate a linear address based on instructions received from said scheduler, said AGU including a first adder to add a product of an index and a scaling factor to an offset and a segment base during a first clock cycle, and a second adder to add output of the first adder with a base during a second clock cycle.
2 more elements
A method comprising:
- first adding a product of an index and a scaling factor to an offset and a segment base during a first clock cycle;
- and
- second adding the result of the first adding with a base during a second clock cycle.
Dependencies are inferred from the claim text.