S-band low-noise amplifier with self-adjusting bias for improved power consumption and dynamic range in a mobile environment

An amplifier comprising:

• at least one Field Effect Transistor (FET) receiving at its gate an input signal from an external source and amplifying this input signal in accordance with its drain-source bias voltage VDS to produce at its drain an amplified output signal;
• a power detector circuit monitoring the amplified output signal to produce a detected-power voltage signal VDD;
• and
• a dynamic bias control circuit comparing the detected-power signal VDD to the drain-source bias voltage VDS to vary a gate-to-source voltage bias VGS of the input signal, actively moving a load line of the FET so as to cause the FET to consume more power when the amplified output signal is large;
• wherein when the amplified output signal is large because of a presence of a strong jammer component of the input signal, then the moved load line of the at least one FET will cause the FET to draw more current decreasing noise figure while increasing gain, and will cause the amplifier of which the at least one FET forms a part to reach a new steady state with higher power and improved linearity;
• wherein, however, when no strong jammer component of the input signal is present, and when the amplified output signal is correspondingly not large, then the FET, and the amplifier of which it forms a part, will conserve power;
• wherein a self-adjusting bias of the at least one FET results in improved power consumption and improved dynamic range in an environment where exists occasional strong jammer signals.

A circuit for detecting a peak power of an a.c. signal, the peak power detector circuit comprising:

• a resistive voltage divider, located between a voltage source and ground, producing a reference voltage signal;
• a diode connecting at its cathode to both the a.c. signal and to the reference voltage signal;
• and
• an envelope detector connected both to the anode of the diode and to the reference voltage;
• wherein output of the detector circuit appears across the envelope detector;
• wherein when the a.c. signal is zero then the detector circuit output is equal to the reference voltage;
• wherein when the a.c. signal is not zero then the detector circuit output is equal to a sum of (i) the reference voltage, and (ii) a voltage of an envelope of the a.c. signal, which voltage of the envelope of the a.c. signal is equivalent to the power of the a.c. signal.