Digital cancellation of D/A converter noise in pipelined A/D converters

An improvement to the multistage pipelined Analog-to-Digital Converter (ADC), receiving an analog input signal, having

• a plurality of stages, connected one to the next by an interstage amplifier, each stage having
• a flash analog-to-digital converter (ADC), an ADC of the first stage receiving the analog input signal while ADCs of subsequent stages receive analog signals each from a respective interstage amplifier, producing a multi-level digital signal,
• a digital-to-analog converter (DAC) converting an associated produced multi-level digital signal to an associated intermediate analog signal, each intermediate analog signal being fed both to
• a subtractor of the intermediate analog signal from the associated analog signal received by the stage to produce an analog difference signal that is fed to the interstage amplifier of a next following stage, and also to
• a thermometer encoder producing an associated digital output signal;
• wherein the digital output signals of all the plurality of stages are summed to produce an overall ADC digital output signal,
• the improvement wherein the digital-to-analog converter of each of the plurality of stages comprises:
• a digital-to-analog converter (DAC) that is of a dynamic element matching (DEM) type producing, as well as an associated intermediate analog signal, a (i) plurality of random bits and a (ii) plurality of parity bits the DEM-type DAC comprising
• a digital encoder dividing an N-level digital input signal into multiple digital output signals, each digital encoder comprising:
• two or more switching blocks each having a digital input signal and two digital output signals;
• wherein a sum of the two digital output signals equals the digital input signal;
• and
• a converter converting a sum of the multiple digital output signals as arise from all the digital encoder into a nominally equivalent analog signal;
• and
• wherein each of the plurality of stages additionally comprises:
• a Digital Noise Cancellation (DNC) logic circuit, receiving (1) the (i) plurality of random bits and the (ii) plurality of parity bits from the associated DEM-type DAC and (2) a digitized residue sum of the digital output signals of all stages beyond a stage of which the DNC logic circuit is a part, to produce an error estimate for the stage;
• and
• a subtractor of the error estimate from the DNC logic circuits of all stages beyond the first from the digital output signal of the first stage to produce a corrected ADC digital output signal.

In a multistage analog-to-digital converter (ADC) having in each stage (i) a flash analog-to-digital converter (ADC) producing from a received analog signal a digital signal, and (ii) a thermometer encoder producing from the ADC digital signal another digital signal summable with the like digital signals of the encoders of other stages to produce a final ADC digital output signal of the multistage converter, an improvement to each stage comprising:

• enhancements to the DAC of the stage so as to produce, as well as the DAC digital signal, both random bits and parity bits;
• a Digital Noise Cancellation (DNC) logic circuit receiving (1) the random bits and the parity bits from the stage's enhanced ADC, and (2) the digital signal from the stages's thermometer encoder, to produce a stage error signal;
• and
• a subtractor receiving the stage error signal from the DNC logic circuit so as to error correct the ADC digital output signal and transmit it to a next stage, a succession of all stages producing in the final, ADC digital output signal of the multistage converter, an ADC digital output signal that is corrected for, inter alia, signal error rising from component mismatch in the DACs.

A method of correcting in a final digital output signal of a multistage analog-to-digital converter (ADC) error resultant from, inter alia, component mismatch in digital-to-analog converters (DACs) that are within each stage of the multistage ADC, the signal error correction method comprising:

• producing in an enhanced DAC of each stage both (i) random bits and (ii) parity bits as well as a (iii) DAC digital signal;
• producing in a Digital Noise Cancellation (DNC) logic circuit of each stage from the (i) random bits and (ii) parity bits of the stage's enhanced DAC, plus (iv) a digital signal from a thermometer encoder of the stage that has previously encoded an ADC digital signal of the stage, a stage error signal;
• and
• subtracting in a subtractor of each stage the stage's error signal produced in the DNC logic circuit from an ADC digital output signal of the stage, passing onward to a next successive stage the corrected ADC digital output signal until, at the conclusion of all stages the final ADC digital output signal is corrected for, inter alia, error in this final signal rising from component mismatch in the DACs.