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US 6,731,542 B1Granted
Circuit for accurate memory read operations
AssigneeAdvanced Micro Devices, Inc.
InventorsBinh Q. Le, Michael Achter, Lee Cleveland, Chen Pauling
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsBinh Q. Le, Michael Achter, Lee Cleveland, Chen Pauling
Estimating the term…
A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.
A memory circuit arrangement for sensing current in a target cell during a read operation, said memory circuit arrangement comprising:
A memory circuit arrangement comprising:
A memory circuit arrangement for sensing current in a target cell during a read operation, said memory circuit arrangement comprising said target cell having a first bit line connected to ground, said target cell having a second bit line connected to a sensing circuit, said memory circuit arrangement being characterized by:
Dependencies are inferred from the claim text.