Level shifter

A level shifter comprising:

• a current mirror circuit;
• a differential circuit having said current mirror circuit as a load;
• a first current source for supplying current to said differential circuit;
• a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
• a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
• and
• second and third current sources for supplying current to said first and second transistors, respectively,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal from said first transistor is input to said differential circuit,
• wherein a second input signal is input to a second source region of said second transistor, and
• wherein a second output signal from said second transistor is input to said differential circuit.

A level shifter comprising:

• a current mirror circuit;
• a differential circuit having said current mirror circuit as a load;
• a first current source for supplying current to said differential circuit;
• a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
• a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
• and
• second and third current sources for supplying current to said first and second transistors, respectively,
• wherein said differential circuit comprises third and fourth transistors,
• wherein said first drain region of said first transistor and a third gate electrode of said third transistor are electrically connected to each other,
• wherein said second drain region of said second transistor and a fourth gate electrode of said fourth transistor are electrically connected to each other,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal is input to a third gate electrode of said third transistor,
• wherein a second input signal is input to a second source region of said second transistor, and
• wherein a second output signal is input to a fourth gate electrode of said fourth transistor.

A level shifter comprising:

• a first transistor of a first conductive type, having a first gate electrode and a first drain region thereof being electrically connected to each other;
• a second transistor of said first conductive type, having a second gate electrode and a second drain region thereof being electrically connected to each other;
• a differential circuit comprising a third transistor of said first conductive type and a fourth transistor of said first conductive type;
• a current mirror circuit comprising a fifth transistor of a second conductive type and a sixth transistor of said second conductive type, said a fifth gate electrode and a fifth drain region of said fifth transistor being connected to each other;
• a seventh transistor of said first conductive type for electrically connecting said differential circuit and a first current source;
• an eighth transistor of said second conductive type for electrically connecting said fifth transistor and a second current source;
• a ninth transistor of said second conductive type for electrically connecting said sixth transistor and a third current source;
• and
• a power supply portion for supplying potential to gate electrodes of said seventh, eighth, and ninth transistors,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal from said first transistor is input to a third gate electrode of said third transistor,
• wherein a second input signal is input to a second source region of said second transistor, and
• wherein a second output signal from said second transistor is input to a fourth gate electrode of said fourth transistor.

A level shifter comprising:

• first and second current mirror circuits;
• a differential circuit electrically connected to said first and second current mirror circuits;
• a first current source for supplying current to said differential circuit;
• a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
• a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
• and
• second and third current sources for supplying current to said first and second transistors, respectively,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal from said first transistor is input to said differential circuit,
• wherein a second input signal is input to a second source region of said second transistor, and
• wherein a second output signal from said second transistor is input to said differential circuit.

A level shifter comprising:

• first and second current mirror circuits;
• a differential circuit electrically connected to said first and second current mirror circuits;
• a first current source for supplying current to said differential circuit;
• a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
• a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
• and
• second and third current sources for supplying current to said first and second transistors, respectively,
• wherein said differential circuit comprises third and fourth transistors,
• wherein said first drain region of said first transistor and a third gate electrode of said third transistor are electrically connected to each other,
• wherein a second drain region of said second transistor and a fourth gate electrode of said fourth transistor are electrically connected to each other,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein said a first output signal from said first transistor is input to a third gate electrode of said third transistor;
• wherein a second input signal is input to a second source region of said second transistor, and
• wherein a second output signal from said second transistor is input to a fourth gate electrode of said fourth transistor.

A level shifter comprising:

• a current mirror circuit;
• a differential circuit having said current mirror circuit as a load;
• a first current source for supplying current to said differential circuit;
• first and second source follower circuits;
• and
• a transistor for reset,
• wherein a first input signal is input to said first source follower circuit,
• wherein a first output signal from said first source follower circuit is input to said differential circuit,
• wherein a second input signal is input to said second source follower circuit,
• wherein a second output signal from said second source follower circuit is input to said differential circuit, and
• wherein current supply by said first current source is blocked by a reset signal input to said transistor for reset, during a period where voltage amplitude of an input signal is not converted.

A level shifter comprising:

• a current mirror circuit;
• a differential circuit having said current mirror circuit as a load;
• a first current source for supplying current to said differential circuit;
• a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
• a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
• and
• second and third current sources for supplying current to said first and second transistors, respectively,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal from said first transistor is input to said differential circuit,
• wherein a second input signal is input to a second source region of said second transistor,
• wherein a second output signal from said second transistor is input to said differential circuit, and
• wherein current supply by said first, second, and third current sources is blocked during a period where voltage amplitude of an input signal is not converted.

A level shifter comprising:

• a first transistor of a first conductive type, having a first gate electrode and a first drain region thereof being connected to each other;
• a second transistor of said first conductive type, having a second gate electrode and a second drain region thereof being connected to each other;
• a differential circuit comprising a third transistor of said first conductive type and a fourth transistor of said first conductive type;
• a current mirror circuit comprising a fifth transistor of a second conductive type having a fifth gate electrode and a fifth drain region being electrically connected to each other, and a sixth transistor of said second conductive type;
• a seventh transistor of said first conductive type for connecting said differential circuit and a first current source;
• an eighth transistor of said second conductive type for electrically connecting said fifth transistor and a second current source;
• a ninth transistor of said second conductive type for electrically connecting said sixth transistor and a third current source;
• a power supply portion for supplying potential to gate electrodes of said seventh, eighth, and ninth transistors;
• a tenth transistor for reset of said second conductive type;
• and
• a eleventh transistor for reset of said first conductive type,
• wherein said first drain region of said first transistor and a third gate electrode of said third transistor are electrically connected to each other,
• wherein said second drain region of said second transistor and a fourth gate electrode of said fourth transistor are electrically connected to each other,
• wherein a tenth source region of said tenth transistor for reset is electrically connected to seventh and eighth source regions of said seventh and eighth transistors, and a tenth drain region of said tenth transistor for reset is electrically connected to seventh and eighth gate electrodes of said seventh and eighth transistors,
• wherein an eleventh source region of said eleventh transistor for reset is electrically connected to a ninth source region of said ninth transistor, and an eleventh drain region of said eleventh transistor for reset is electrically connected to a ninth gate electrode of said ninth transistor,
• wherein a first input signal is input to a first source region of said first transistor,
• wherein a first output signal from said first transistor is input to said third gate electrode of said third transistor,
• wherein a second input signal is input to a second source region of said second transistor,
• wherein a second output signal from said second transistor is input to said fourth gate electrode of said fourth transistor, and
• wherein during a period where voltage amplitude of an input signal is not converted, current supply is blocked by a reset signal input to said tenth and eleventh transistors for reset, and by making said seventh, eighth, and ninth transistors in a nonconductive state.