Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks

A method of forming a DRAM array comprising:

• etching capacitor contact openings and bit line contact openings relative to continuous active substrate areas having a plurality of conductive lines formed thereatop, at least some of the conductive lines constituting active area isolation lines over the continuous active areas;
• forming a plurality of plugs comprising conductive material relative to the capacitor contact openings and the bit line contact openings, individual plugs being in electrical communication with the substrate;
• and
• forming DRAM capacitors and bit lines over the substrate, individual capacitors and individual bit lines being in electrical communication with individual respective plugs.

A method of forming an integrated circuitry memory device comprising:

• forming insulative material over a plurality of conductive lines over at least one continuous active area formed atop a substrate, at least some of the plurality of lines being isolation lines;
• etching openings through the insulative material and exposing selected active area portions, the exposing defining both capacitor contact openings and bit line contact openings;
• and
• forming conductive material over the substrate, within the openings and in electrical communication with the selected active area portions.

A method of forming an integrated circuitry memory device comprising:

• forming a first insulative layer over an array which is supported relative to a semiconductive substrate, the array having a plurality of continuous active areas, the first insulative layer having an outer surface;
• forming openings in the first insulative layer to expose active area portions, the openings defining both capacitor contact openings and bit line contact openings;
• forming isolated conductive material plugs over the array and within the openings, the conductive material being in electrical communication with associated active area portions;
• forming a second insulative layer over the array;
• removing material of the second insulative layer over the bit line contact openings to expose associated plugs of conductive material therewithin;
• forming a plurality of conductive bit lines over the array, individual bit lines being operably associated with individual continuous active areas and in electrical communication with individual respective plugs of conductive material within the bit line contact openings;
• forming a third insulative layer over the array;
• and
• removing material of the third insulative layer over the capacitor contact openings to expose associated plugs of conductive material therewithin.

A method of forming a DRAM array comprising:

• forming a plurality of conductive lines over a plurality of continuous active areas formed atop a substrate, at least some of the conductive lines constituting active area isolation lines over the continuous active areas;
• etching capacitor contact openings and bit line contact openings relative to the continuous active areas;
• forming a plurality of plugs comprising conductive material relative to the capacitor contact openings and the bit line contact openings, individual plugs being in electrical communication with the substrate;
• and
• forming DRAM capacitors and bit lines over the substrate, individual capacitors and individual bit lines being in electrical communication with individual respective plugs, wherein forming a plurality of conductive lines comprises forming word lines and the active area isolation lines over the plurality of continuous active areas.

A method of forming a DRAM array comprising:

• forming a plurality of conductive lines over a plurality of continuous active areas formed atop a substrate, at least some of the conductive lines constituting active area isolation lines over the continuous active areas;
• etching capacitor contact openings and bit line contact openings relative to the continuous active areas;
• forming a plurality of plugs comprising conductive material relative to the capacitor contact openings and the bit line contact openings, individual plugs being in electrical communication with the substrate;
• and
• forming DRAM capacitors and bit lines over the substrate, individual capacitors and individual bit lines being in electrical communication with individual respective plugs, wherein forming DRAM capacitors and bit lines over the substrate comprises forming DRAM capacitors and bit lines over word lines and the active area isolation lines.

A method of forming a DRAM array comprising:

• forming a plurality of conductive lines over a plurality of continuous active areas formed atop a substrate, at least some of the conductive lines constituting active area isolation lines over the continuous active areas;
• etching capacitor contact openings and bit line contact openings relative to the continuous active areas;
• forming a plurality of plugs comprising conductive material relative to the capacitor contact openings and the bit line contact openings, individual plugs being in electrical communication with the substrate;
• and
• forming DRAM capacitors and bit lines over the substrate, individual capacitors and individual bit lines being in electrical communication with individual respective plugs, further comprising forming an insulative layer over word lines and the active area isolation lines formed on the substrate, wherein etching capacitor contact openings and bit line contact openings comprises etching capacitor contact openings through the insulating layer over the continuous active areas.

A method of forming an integrated circuitry memory device comprising:

• forming a plurality of conductive lines over at least one continuous active area formed atop a substrate, selected individual conductive lines being configured to provide electrical isolation between adjacent portions of the at least one continuous active area;
• forming insulative material over the substrate;
• etching openings through the insulative material and exposing selected active area portions, the exposing defining both capacitor contact openings and bit line contact openings;
• and
• forming conductive material over the substrate, within the openings and in electrical communication with the selected active area portions, wherein forming a plurality of conductive lines comprises forming word lines and active area isolation lines over the at least one continuous active area.

A method of forming an integrated circuitry memory device comprising:

• forming a plurality of conductive lines over at least one continuous active area formed atop a substrate, selected individual conductive lines being configured to provide electrical isolation between adjacent portions of the at least one continuous active area;
• forming insulative material over the substrate;
• etching openings through the insulative material and exposing selected active area portions, the exposing defining both capacitor contact openings and bit line contact openings;
• and
• forming conductive material over the substrate, within the openings and in electrical communication with the selected active area portions, further comprising forming DRAM capacitors and bit lines over the substrate.

A method of forming an integrated circuitry memory device comprising:

• forming a first insulative layer over an array which is supported relative to a semiconductive substrate, the array having a plurality of continuous active areas and a plurality of conductive lines operably associated therewith, at least some of the conductive lines constituting active area isolation lines over the continuous active areas, the first insulative layer having an outer surface;
• forming openings in the first insulative layer to expose active area portions, the openings defining both capacitor contact openings and bit line contact openings;
• forming isolated conductive material plugs over the array and within the openings, the conductive material being in electrical communication with associated active area portions;
• forming a second insulative layer over the array;
• removing material of the second insulative layer over the bit line contact openings to expose associated plugs of conductive material therewithin;
• forming a plurality of conductive bit lines over the array, individual bit lines being operably associated with individual continuous active areas and in electrical communication with individual respective plugs of conductive material within the bit line contact openings;
• forming a third insulative layer over the array;
• and
• removing material of the third insulative layer over the capacitor contact openings to expose associated plugs of conductive material therewithin, wherein forming the first insulative layer comprises forming the first insulative layer over word lines and active area isolation lines.

A method of forming an integrated circuitry memory device comprising:

• forming a first insulative layer over an array which is supported relative to a semiconductive substrate, the array having a plurality of continuous active areas and a plurality of conductive lines operably associated therewith, at least some of the conductive lines constituting active area isolation lines over the continuous active areas, the first insulative layer having an outer surface;
• forming openings in the first insulative layer to expose active area portions, the openings defining both capacitor contact openings and bit line contact openings;
• forming isolated conductive material plugs over the array and within the openings, the conductive material being in electrical communication with associated active area portions;
• forming a second insulative layer over the array;
• removing material of the second insulative layer over the bit line contact openings to expose associated plugs of conductive material therewithin;
• forming a plurality of conductive bit lines over the array, individual bit lines being operably associated with individual continuous active areas and in electrical communication with individual respective plugs of conductive material within the bit line contact openings;
• forming a third insulative layer over the array;
• and
• removing material of the third insulative layer over the capacitor contact openings to expose associated plugs of conductive material therewithin, further comprising forming DRAM capacitors and bit lines over the substrate.