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US 6,725,449 B1Granted
Semiconductor test program debugging apparatus
AssigneeAdvantest Corporation
InventorsYoshinori Maeda, Hironori Maeda, Tadashi Oda
Life of this patent
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Abstract
A semiconductor test program debugging apparatus is disclosed to which data concerning a packet input to and output from the packet transfer memory device is supplied, and which extracts a part corresponding to the packet from data input to and output from the memory device with response to a test signal generated by a tester simulator and displays the details of the part.
Claims6
A semiconductor test program debugging apparatus, comprising:
- tester simulation unit for simulating the operation of a semiconductor test apparatus by generating a test signal in a simulative manner based on a test program provided for a packet transfer memory device;
- data supply unit for supplying data concerning a packet input to and output from said packet transfer memory device;
- and
- packet extraction and display unit for, based on said data supplied by said data supply unit, extracting a part corresponding to said packet from said test signal generated by said tester simulation unit and displaying the content thereof.
1 more element
Dependencies are inferred from the claim text.