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AssigneeLattice Semiconductor Corporation
InventorsRichard T. Cote, Brenda Nguyen, Xuan D. Pham, Bradley A. Sharpe-Geisler
Estimating the term…
Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.
A method of defining an interconnect-challenging sequence of unique sequencer states for testing the operability of a plurality of under-test, programmable interconnect resources (IRUT's) where said IRUT's are used to feedback a previously stored, sequencer state to inputs of a programmable sequencer for thereby producing, if the under-test IRUT's are in operative rather than defective condition, a next expected state of the programmable sequencer, said method comprising:
A re-programmably programmed sequencer that uses a plurality of under-test, programmable interconnect resources (IRUT's) to feedback previously stored, sequencer states to inputs of the sequencer for thereby producing, if the under-test IRUT's are in operative rather than in a faulty condition, an expected interconnect-challenging sequence of unique sequencer states for testing the operability of a plurality of under-test, programmable interconnect resources (IRUT's), where said re-programmably programmed sequencer is programmed to:
A manufactured instructing signal which is loadable into an FPGA for defining in the FPGA, a re-programmably programmed sequencer that uses a plurality of under-test, programmable interconnect resources (IRUT's) to feedback previously stored, sequencer states to inputs of the sequencer for thereby producing, if the under-test IRUT's are in operative rather than in a faulty condition, an expected interconnect-challenging sequence of unique sequencer states for testing the operability of a plurality of under-test, programmable interconnect resources (IRUT's), where said re-programmably programmed sequencer is programmed to:
A manufactured instructing signal which is loadable into an instructable computing machine for causing the computing machine to carry out an interconnect verification operation which includes the formation within an under-test FPGA of a programmed sequencer that uses a plurality of under-test, programmable interconnect resources (IRUT's) to feedback previously stored, sequencer states to inputs of the sequencer for thereby producing, if the under-test IRUT's are in operative rather than in a faulty condition, an expected interconnect-challenging sequence of unique sequencer states for testing the operability of a plurality of under-test, programmable interconnect resources (IRUT's), where said re-programmably programmed sequencer is programmed to:
Dependencies are inferred from the claim text.