Method of automated design and checking for ESD robustness

A chip design method comprising the steps of:

• a) retrieving a power route pattern induction;
• b) identifying power and power return connections;
• c) routing each said power and each said power return connection, each said routed connection meeting wire width and maximum resistance constraints in said retrieved power route pattern instruction, wherein the routing step includes the steps of:
• it providing an ESDxx cell;
• and
• ii) connecting said ESDxx cell between power rails and sower return rails for at least two different power supplies;
• and
• d) checking said wired integrated circuit.

A chip design method comprising the steps of:

• a) retrieving identifications and placement constraints of a plurality of I/O cells and a plurality of ESDxx cells;
• b) providing said plurality of I/O cells for placement according to said placement constraints;
• c) placing each of said plurality of ESDxx cells with said plurality of I/O cells;
• d) connecting each of said placed ESDxx cells between power rails and power return rails for at least two different power supplies;
• and
• e) checking said wired integrated circuit.

A system for integrated circuit chip design comprising:

• means for retrieving net constraints from technology data;
• means for placing a plurality of I/O cells;
• means for placing a plurality of ESDxx cells;
• means for connecting each of said placed I/O cells to an I/O pad according to said retrieved net constraints;
• and
• means for connecting said placed ESDxx cells between power rails and power return rails for at least two different power supplies.

A computer readable medium comprising instructions for a computer implemented chip design method, said method comprising the steps of:

• a) retrieving a wire width constraints from technology data for an I/O cell;
• b) retrieving a maximum resistance constraint from said technology data for said I/O cell;
• c) propagating said wiring width constraint and said maximum resistance constraint to net design data for said chip;
• d) generating said chip, comprising the steps of:
• constraining connections between said I/O cell and an associated pad by said propagated constraints;
• providing a plurality of ESDxx cells;
• and
• connecting said plurality of ESDxx cells between power rails and power return rails for at least two different power supplies;
• and
• e) checking said wired integrated circuit.