Method and program product for completing a circuit design having embedded test structures

A sign-off method for use in verifying embedded test circuitry in a circuit design having circuit modules with embedded test circuitry, said method comprising:

• for each circuit module in said design containing embedded test circuitry, repeating the following steps, in sequence, beginning with a circuit module at a lowest level of hierarchy and ending with a circuit module at a highest level of hierarchy of said circuit design:
• extracting a description of all embedded test circuitry in said circuit module from a final circuit module description file, creating a test connection map file specifying connections between inputs and outputs of said embedded test circuitry and ports of said circuit module, and verifying the correctness of said connections, including, for signed-off circuit modules, using a test connection map created for said signed-off circuit modules and verifying connections between circuit module ports and ports of said signed-off circuit modules;
• creating a verification configuration file containing, for each said embedded test circuit, a specific verification section containing parameters for use in generating a sequence of simulation steps for verifying proper operation of said embedded test circuits in said circuit module;
• for a circuit module containing logic test circuitry which has not been signed-off, verifying that each said logic test circuitry complies with logic test structure design rules and creating logic test vectors and a reference signature for each said logic test structure;
• performing a formal verification of said circuit modules which have not been signed-off;
• performing a static timing analysis of said final circuit module description which have not been signed-off to verify timing correctness of embedded test circuitry;
• creating a hand-off database containing all intermediate files related to said embedded test circuitry in said circuit module including said test connection map file, said configuration file, and embedded test circuitry information files;
• generating a sign-off simulation test bench for each specific verification section of said configuration file for each said sequence of simulation steps using embedded test circuitry connections specified in said test connection map file;
• executing said test benches to simulate all embedded test circuitry in said circuit module;
• and, following optimization and layout of said circuit,
• creating manufacturing test patterns.