# US 6,725,404 B1 · Evaluation of interconnect reliability using propagation delay through interconnect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,725,404 B1 - Document ID: US6725404B1 - Status: Granted - Kind: B1 - Application number: 09/580,782 - Filed: 2000-05-26 - Granted: 2004-04-20 - Earliest claimed: 2000-05-26 - Assignees: International Business Machines Corporation - Inventors: Apurba Choudhury; Thomas Wen Liang - Web page: https://patentgrep.com/patent/US6725404B1 ## CPC - G01R 31/69: of terminals at the end of a cable or a wire harness; of plugs; of sockets, e.g. wall sockets or power sockets in appliances - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An apparatus and method for reliability testing an electrical connector for an unacceptable propagation delay. The propagation delay is detected in a transmitted test signal through the electrical connector in comparison to a reference signal having a known delay. A failure signal occurs in response to the transmitted test signal failing to transition before a corresponding transition in the reference signal. The apparatus and method is extendable to a plurality of conductor paths in the electrical connector, such as a parallel communication digital data bus. Moreover, the known delay in the reference signal is selectable for adjusting an allowable propagation delay criteria for applications with different data rate requirements. ## Claims ### Claim 1 A test apparatus for testing an electrical connector, the electrical connector including a first connector contact and a second connector contact, the first connector contact being in electrical communication with the second connector contact, the test apparatus comprising: a connector interface including a first test contact and a second test contact, the connector interface configured to electrically couple the first test contact to the first connector contact and to electrically couple the second test contact to the second connector contact; and a test circuit arrangement configured to determine the reliability of the electrical connector by determining propagation delay along a test signal path incorporating the electrical connector, wherein the test circuit arrangement includes: a test signal generator operable for generating a test signal, the test signal path coupled to the test signal generator and configured to transmit the test signal through the electrical connector via the connector interface to produce a transmitted signal; a reference signal generator operable for generating a reference signal; and a delay detector coupled to the test signal path and the reference signal generator, the delay detector operable for detecting a delay in the transmitted signal relative to the reference signal. ### Claim 2 (depends on 1) The test apparatus of claim 1, wherein the reference signal is generated by the test signal generator, the reference signal including a known delay. ### Claim 3 (depends on 2) The test apparatus of claim 2, wherein the reference signal generator comprises a reference path coupling the test signal generator to the delay detector, the reference path including a reference delay operable to impart the known delay to the test signal to produce the reference signal. ### Claim 4 (depends on 3) The test apparatus of claim 3, wherein the reference delay includes one of a low pass filter and a length of transmission line. ### Claim 5 (depends on 3) The test apparatus of claim 3, wherein the delay detector includes a comparator operable for outputting a fault signal in response to a delay in the transmitted signal exceeding the known delay in the reference signal. ### Claim 6 (depends on 3) The test apparatus of claim 3, wherein the test signal generator comprises a pulse generator, the test signal comprising a digital pulse signal. ### Claim 7 (depends on 6) The test apparatus of claim 6, wherein the test signal path further includes a digital inverter operable to invert the test signal, the comparator comprising a D flip-flop including a Data input, a Clock input, and a Q output, the Data input coupled to the test signal path to receive the transmitted signal, the Clock input coupled to the reference path to receive the reference signal, the Q output providing the fault signal in response to an amplitude transition of the transmitted signal subsequent to an amplitude transition of the reference signal. ### Claim 8 (depends on 7) The test apparatus of claim 7, further comprising an indicator latch operable to output a latched fault signal in response to the fault signal of the comparator. ### Claim 9 (depends on 8) The test apparatus of claim 8, wherein the indicator latch comprises a D flip-flop including a Data input, Clock input, and a Q output; the Data input coupled to a logic 1 signal, the Clock input coupled to receive the fault signal from the comparator D flip-flop, the indicator latch D flip-flop operable to output the latched fault signal at the Q output in response to the fault signal. ### Claim 10 (depends on 9) The test apparatus of claim 9, further comprising an indicator responsive to the latched fault signal. ### Claim 11 (depends on 10) The test apparatus of claim 10, wherein the indicator comprises a Light Emitting Diode (LED). ### Claim 12 (depends on 6) The test apparatus of claim 6, wherein the test signal path includes a first transmission line emulator, and wherein the reference path includes a second transmission line emulator. ### Claim 13 (depends on 12) The test apparatus of claim 12, wherein each of the first and second transmission line emulators respectively comprises a buffer and resistor in a series combination. ### Claim 14 (depends on 1) The test apparatus of claim 1, further including a test enable circuit arrangement operable to selectably transmit the test signal through the electrical connector via the connector interface. ### Claim 15 (depends on 1) The test apparatus of claim 1, wherein the electrical connector comprises a digital bus electrical connector, the digital bus electrical connector including a plurality of first connector contacts and a corresponding plurality of second connector contacts in electrical communication therewith, the connector interface including corresponding pluralities of first and second test contacts, the test circuit arrangement including a corresponding plurality of test signal paths and delay detectors for each pair of the pluralities of first and second connector contacts. ### Claim 16 A method of determining the reliability of an electrical connector, the electrical connector including a first connector contact and a second connector contact, the first connector contact in electrical communication with the second connector contact, the method comprising: interfacing a test signal path to the first and second connector contacts of the electrical connector; transmitting a test signal along the test signal path to the first connector contact; and detecting a propagation delay in a transmitted signal from the second connector contact, wherein detecting the propagation delay in the transmitted signal includes comparing the transmitted signal to a reference signal. ### Claim 17 A method of determining the reliability of an electrical connector, the electrical connector including a first connector contact and a second connector contact, the first connector contact in electrical communication with the second connector contact, the method comprising: interfacing a test signal path to the first and second connector contacts of the electrical connector; transmitting a test signal along the test signal path to the first connector contact; detecting a propagation delay in a transmitted signal from the second connector contact, wherein detecting the propagation delay in the transmitted signal includes comparing the transmitted signal to a reference signal; transmitting the test signal along a reference path; and delaying the test signal by a known delay to form the reference signal. ### Claim 18 (depends on 17) The method of claim 17, wherein delaying the test signal includes low pass filtering the test signal. ### Claim 19 (depends on 17) The method of claim 17, wherein the test signal comprises a pulsed signal.