Clock modes for a debug port with on the fly clock switching

An integrated circuit comprising:

• a function clock circuit generating a function clock signal;
• an operation circuit connected to said function clock circuit operating in synchronism with said function clock;
• a trace trigger circuit connected to said function clock circuit and said operation circuit, said trace trigger circuit triggering trace of operation of said operation circuit upon detection of a predetermined condition within said operation circuit;
• a clock circuit including
• at least one externally writeable clock control register, said clock control register including at least a mode field indicating clock mode,
• a reference clock input for receiving a reference clock signal,
• an controllable oscillator circuit generating an oscillator clock signal,
• a first multiplexer having a first input connected to said function clock circuit for receiving said function clock signal, a second input connected to said reference clock input for receiving said reference clock signal, a third input connected to said controllable clock circuit for receiving said oscillator clock signal, a control input connected to said clock control register and an output, said first multiplexer selecting at said output one of said function clock signal, said reference clock input and said oscillator clock signal corresponding to said clock mode indicated by said mode field of said clock control register,
• a second multiplexer having a first input connected to connected to said reference clock input for receiving said reference clock signal, a second input connected to said controllable clock circuit for receiving said oscillator clock signal, a control input connected to said clock control register and an output, said second multiplexer selecting at said output one of said reference clock signal and said oscillator clock signal corresponding to said clock mode indicated by said mode field of said clock control register,
• a comparison circuit connected to said clock control register, said first multiplexer and said second multiplexer controlling a frequency of said controllable oscillator circuit to achieve a frequency match between said clock signal selected by said first multiplexer and said clock signal selected by said second multiplexer;
• a trace first-in-first-out buffer having an input connected to said function clock circuit and said operation circuit for storing trace data in synchronism with said function clock signal and an output connected to said clock circuit for outputting trace data in synchronism with said oscillator clock signal;
• and
• a trace output port connected to said controllable clock circuit and said output of said trace first-in-first-out buffer outputting trace data in synchronism with said oscillator clock signal.