Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
AssigneeLSI Logic Corporation
InventorsAlexander Tetelbaum, Rajiv Kapur
Life of this patent
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Abstract
A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
Claims7
A method of clock buffer placement for minimizing clock skew comprising the steps of:
- (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group;
- (b) placing a clock buffer at an initial location in the trunk delay model;
- (c) estimating a clock skew and an insertion delay from the trunk delay model;
- (d) checking whether the clock skew exceeds a clock skew limit;
- and
- (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
Dependencies are inferred from the claim text.