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US 6,725,388 B1Granted
Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains
AssigneeIntel Corporation
InventorDean S. Susnow
Life of this patent
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Abstract
Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.
Claims17
A method comprising:
- inserting unique coded command signals into a data stream transmitted from a first asynchronous clock domain to a second asynchronous clock domain, wherein the unique coded command signals implement a link synchronization method;
- passing the unique coded command signals without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer;
- decoding the unique coded command signals in receiver circuitry in the second asynchronous clock domain;
- controlling process circuitry that comprises a transmitter in the second asynchronous clock domain according to the decoded command signals;
- generating and outputting, by the receiver circuitry control signals that instruct the transmitter to transmit a sequence of IDLE characters, wherein at least one of the control signals is a sticky control signal that instructs the transmitter to transmit IDLE characters until there is a change in the state of the sticky control signal;
- and
- transmitting, with the transmitter, the sequence of IDLE characters to establish link synchronization.
4 more elements
An apparatus comprising:
- a physical logic block coupled to receive data from link data and to operate in a link clock domain;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in a core clock domain, wherein a plurality of respective command signals are to be provided to said elastic buffer, each one of said plurality of respective command signals corresponding to a different state of a link synchronization state machine;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method that consists of the transmission of IDLE-1 and IDLE-2 characters;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals received from said receiver logic block, said control signals being derived from the synchronous command signals.
2 more elements
An apparatus comprising:
- a physical logic block coupled to receive data from link data and to operate in a link clock domain;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in a core clock domain, wherein a plurality of respective command signals are to be provided to said elastic buffer, each one of said plurality of respective command signals corresponding to a different state of a link synchronization state machine;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method that consists of the transmission of IDLE-1 and IDLE-2 characters, said receiver logic block to output two control signals, the values of said two control signals corresponding to the transmission of IDLE-1 or IDLE-2 characters according to the link synchronization method;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals received from said receiver logic block, said control signals being derived from the synchronous command signals.
2 more elements
A network, comprising:
- a host system;
- at least one remote system;
- a switched fabric comprising a plurality of switches which interconnect said host system via a virtual interface expansion bridge to said remote system along a serial communication link, and
- a physical logic block included in said virtual interface expansion bridge to receive data from said serial communication link and to operate in the clock domain of said communication link;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in the core clock domain, wherein a plurality of respective command signals are to be provided to said elastic buffer, each one of said plurality of respective command signals corresponding to a different state of a link synchronization state machine;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method, that consists of the transmission of IDLE-1 and IDLE-2 characters;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals received from said receiver logic, said control signals being derived from the synchronous command signals.
5 more elements
A network, comprising:
- a host system;
- at least one remote system;
- a switched fabric comprising a plurality of switches which interconnect said host system via a virtual interface expansion bridge to said remote system along a serial communication link, and
- a physical logic block included in said virtual interface expansion bridge to receive data from said serial communication link and to operate in the clock domain of said communication link;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in the core clock domain, wherein a plurality of respective command signals are to be provided to said elastic buffer, each one of said plurality of respective command signals corresponding to a different state of a link synchronization state machine;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method, that consists of the transmission of IDLE-1 and IDLE-2 characters, said receiver logic block to output two control signals, the values of said two control signals corresponding to the transmission of IDLE-1 or IDLE-2 characters according to the link synchronization method;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals received from said receiver logic, said control signals being derived from the synchronous command signals.
5 more elements
An apparatus comprising:
- a physical logic block coupled to receive data from link data and to operate in a link clock domain;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in a core clock domain;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals to be received from said receiver logic block, said control signals being derived from the synchronous command signals, wherein at least one of the control signals is a sticky control signal that is to instruct the transmitter logic block to transmit IDLE characters until there is a change in the state of the sticky control signal.
2 more elements
A network, comprising:
- a host system;
- at least one remote system;
- a switched fabric comprising a plurality of switches which interconnect said host system via a virtual interface expansion bridge to said remote system along a serial communication link, and
- a physical logic block included in said virtual interface expansion bridge to receive data from said serial communication link and to operate in the clock domain of said communication link;
- an elastic buffer to receive data from said physical logic block in the link clock domain and to output data in the core clock domain;
- a receiver logic block to receive and decode synchronous command signals in the core clock domain relating to a link synchronization method;
- and
- a transmitter logic block to transmit signals to establish link synchronization according to control signals received from said receiver logic, said control signals being derived from the synchronous command signals, wherein at least one of the control signals is a sticky control signal that is to instruct the transmitter logic block to transmit IDLE characters until there is a change in the state of the sticky control signal.
5 more elements
Dependencies are inferred from the claim text.