Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed

A method of creating repeatability in a system with a common clock signal by creating repeatability in arbitration comprising:

• receiving a common clock signal after the system becomes idle, the common clock signal having a plurality of clock edges;
• sending a reset message from a processor to a reset agent associated with an arbiter that performs a function, wherein said function is different on succeeding common clock signals;
• sending a reset signal from the reset agent to the arbiter at a first clock edge of the common clock signal;
• and
• resetting the arbiter at a next clock edge of the common clock signal.

A computer system for ensuring repeatability of a machine state during testing comprising:

• an arbiter that performs a function that requires a plurality of clock cycles;
• a reset agent connected to the arbiter;
• a global framing clock having a lower frequency than a system clock and having a clock edge that corresponds to the clock edge of the system clock;
• and
• a processor connected to the reset agent, which processor executes test code, wherein the processor:
• receives a system signal when the system becomes idle at a first clock edge of the global framing clock;
• and
• sends a reset message to the reset agent after receiving the system signal, which message causes the arbiter to reset at a next clock edge of the global framing clock.