Method and apparatus for enabling a wake-up event by modifying a second register to enable a second wake-up event responsive to detecting entry of data in a first register
AssigneeIntel Corporation
InventorsJohn P. Lambino, James H. Ewertz
Life of this patent
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Abstract
A method and apparatus provides hardware-configured wake-up events for a computer operating system compliant with an advanced configuration and power interface (ACPI) protocol without requiring additional hardware. The method and apparatus includes generation of a system management interrupt (SMI) during normal ACPI working-to-sleep transition allowing a basic input-output system (BIOS) circuit to enable additional wake-up events independent of the computer operating system.
Claims15
A method for allowing a computer to wakeup, comprising:
- detecting entry of data into a first register to enter a non-working state enabling a first wake-up event for a computer;
- modifying data in a second register in response to a system management interrupt being generated, and using basic input-output system instructions to place data into the second register to enable a second wake-up event from said non-working state in response to said detecting entry of data into the first register, wherein the second resister includes a pointer in a device table;
- and
- allowing entry into said non-working state for the computer.
An article of manufacture comprising a computer-readable medium having stored thereon instructions adapted to be executed by a circuit, the instructions which, when executed, cause the circuit to:
- detect entry of data into a first register enter a non-working state enabling a first wake-up
- event for a computer;
- modify data in a second register in response to a system interrupt and use basic input-output system instructions to enter data into the second register to enable a second wake-up event from said non-working state in response to the detection of entry of data into the first register, wherein the second register has a pointer in a device table;
- and
- allow entry into said non-working state for the computer.
A computer system, comprising:
- a plurality of registers to store data for wake-up events for a computer from a nonworking state, each having a pointer to a device table;
- an I/O memory, including said plurality of registers, to store I/O addresses for hardware enabled to wake-up the computer from the non-working state;
- a processor, operatively coupled to said memory, for entering data in a first portion of said plurality of registers and reading the I/O addresses to enable a first wake-up event, and for placing the computer in the non-working state;
- a basic input-output system instruction circuit, operatively coupled to at least a second portion of said plurality of registers, to modify the data in said second portion, to enable a second wake-up event, in response to a system management interrupt generated by said processor.
Dependencies are inferred from the claim text.