Circuit for allowing data return in dual-data formats
AssigneeHewlett-Packard Development Company, L.P.
InventorsJames C. Farmer, Kent A. Dickey
Life of this patent
Estimating the term…
Abstract
A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.
Claims20
A method of reconfiguring data for communication between processors and a memory, comprising:
- receiving a plurality of bytes in a particular dual-data format associated with a first processor or a second processor, the first processor and the memory are in the same dual-data format and the second processor and the memory are in a different dual-data format;
- receiving a control signal via one bit of a multi-bit address bus set to a first state for the first processor or set to a second state for the second processor;
- and
- selectively reconfiguring the bytes based upon the control signal, including transmitting the data in the particular dual-data format if the control signal is set to the first state and reconfiguring the particular dual-data format of the bytes if the control signal is set to the second state.
An interface for transmitting and selectively reconfiguring data between processors and a memory, comprising:
- a data bus for receiving a plurality of bytes in a particular dual-data format associated with a first processor or a second processor, the first processor and the memory are in the same dual-data format and the second processor and the memory are in a different dual-data format;
- a control terminal for receiving a control signal as one bit of a multi-bit address bus which is set to a first state for the first processor or set to a second state for the second processor;
- and
- control logic, coupled to the data bus and the control terminal, that transmits the data in the particular dual-data format if the control signal is set to the first state and reconfiguring the particular dual-data format of the bytes if the control signal is set to the second state.
An interface for transmitting and selectively reconfiguring data between processors and a memory, comprising:
- a first data bus for receiving bytes in a particular dual-data format associated with a first processor or a second processor, the first processor and the memory are in the same dual-data format and the second processor and the memory are in a different dual-data format;
- a second data bus for outputting bytes;
- a control terminal coupled to one bit of a multi-bit address bus for receiving a control signal set to a first state for the first processor or set to a second state for the second processor;
- and
- a logic circuit, coupled to the first data bus, the second data bus, and the control terminal, wherein the logic circuit receives the bytes from the first data bus, selectively reconfigures the particular dual-data format of the received bytes based upon the control signal, and outputs the selectively reconfigured bytes on the second bus.
Dependencies are inferred from the claim text.