System for executing a post having primary and secondary subsets, wherein the secondary subset is executed subsequently to the primary subset in the background setting
AssigneeGateway, Inc.
InventorFrank W. Liebenow
Life of this patent
Estimating the term…
Abstract
A method and apparatus for executing a power on self test includes executing a primary subset of POST tests during initial startup of a computer, and executing a secondary subset of non-essential POST tests transparent to a user at a later time. The secondary subset of POST tests may be performed after a period of computer inactivity.
Claims31
A method of executing a power on self test (POST), comprising:
- selecting a primary subset of POST tests to execute during initial POST;
- selecting a secondary subset of POST tests to execute after initial POST;
- executing the primary subset of POST tests during initial POST;
- and
- executing the secondary subset of POST tests in a background setting.
A method for executing a power on self test (POST), comprising:
- executing a primary subset of a full set of POST tests;
- waiting for a predetermined period of inactivity;
- executing a secondary subset of POST tests;
- flagging any test error in the secondary subset of POST tests with a persistent flag;
- adding any of the secondary subset of POST tests with errors to the primary subset of POST tests;
- and
- executing the new primary subset upon a next computer start up.
A computer readable medium comprising computer instructions executable to cause a computer to perform a method comprising:
- selecting a primary subset of POST tests to execute during initial POST;
- selecting a secondary subset of POST tests to execute after initial POST;
- executing the primary subset of POST tests during initial POST;
- and
- executing the secondary subset of POST tests in a background setting.
A computer system, comprising:
- a computer;
- a BIOS chip having encoded thereon instructions for performing a POST test, comprising:
- selecting a primary subset of POST tests to execute during initial POST;
- selecting a secondary subset of POST tests to execute after initial POST;
- executing the primary subset of POST tests during initial POST;
- and
- executing the secondary subset of POST tests in a background setting.
A BIOS chip having instructions coded thereon for performing a method comprising:
- selecting a primary subset of POST tests to execute during initial POST;
- selecting a secondary subset of POST tests to execute during initial POST;
- executing the primary subset of POST tests during initial POST;
- and
- executing the secondary subset of POST tests in a background setting.
Dependencies are inferred from the claim text.