# US 6,725,365 B1 · Branching in a computer system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,725,365 B1 - Document ID: US6725365B1 - Status: Granted - Kind: B1 - Application number: 09/562,551 - Filed: 2000-05-02 - Granted: 2004-04-20 - Earliest claimed: 1999-05-03 - Assignees: STMicroelectronics S.r.l. - Inventors: Andrew Cofler; Stéphane Bouvier - Web page: https://patentgrep.com/patent/US6725365B1 ## CPC - G06F 9/3804: {for branches, e.g. hedging, branch folding} - G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator. ## Claims ### Claim 1 A computer system for executing instructions predicated on guard indicators included in the instructions, the instructions including normal instructions which are executed if the guard indicator is true and branch instructions which are executed if the guard indicator is false, the computer system comprising: instruction supply circuitry; at least one execution unit for receiving instructions from the supply circuitry; branch detection circuitry for detecting a branch instruction, for holding the guard indicator of the branch instruction and for setting a branch shadow mode; means operable in the branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match; and means for disabling the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator. ### Claim 2 (depends on 1) A computer system according to claim 1, which comprises a decoder for decoding the instructions and wherein the branch detection circuitry is located in the decoder. ### Claim 3 (depends on 1) A computer system according to claim 1, which comprises a plurality of parallel execution units for receiving respective said instructions from the instruction supply circuitry, wherein each instruction has a respective guard indicator selected from a set of guard indicators. ### Claim 4 (depends on 3) A computer system according two claim 3, wherein one of said execution units includes a master guard value store containing a master representation of current values for the guard indicators in said set of guard indicators, and another one of said execution units is responsible for executing branch instructions, said other execution unit being operable to request and receive from said master store a guard value for resolving a branch instruction. ### Claim 5 (depends on 1) A computer system according to claim 1, wherein the instruction supply circuitry comprises a control unit which includes a fetch branch address unit for holding a branch target address. ### Claim 6 (depends on 1) A computer system according to claim 1, in which each execution unit comprises a plurality of pipelined stages, with synchronized pipeline cycles for each of the execution units when a plurality of execution units are present. ### Claim 7 (depends on 1) A computer system according to claim 1, which comprises a plurality of pipelined stages for supplying, decoding and executing instructions. ### Claim 8 (depends on 3) A computer system according to claim 3, wherein the execution units include execution pipelines providing access to a data memory, said pipelines including a first set of pipelines for use in executed instructions need for memory access operations, a second set of pipelines arranged to carry out arithmetic operations, thereby providing decoupling of memory access operations from arithmetic operations, and a third pipeline for executing branch instructions. ### Claim 9 (depends on 8) A computer system according to claim 8, wherein the second set of pipelines and the third pipeline share an instruction queue holding instructions awaiting access to the pipelines, the third pipeline having a dedicated slot for holding branch instructions awaiting resolution while instructions from the instruction queue continue to be supplied to the pipelines. ### Claim 10 A method of executing instructions in a computer system predicated on guard indicators included in the instructions, the instructions including normal instructions which are executed the guard indicator is true and branch instructions which are executed if the guard indicator is false, the method comprising: supplying instructions to at least one execution unit; detecting a branch instruction and, responsive to such detection, holding the guard indicator of the branch instruction and setting a branch shadow mode; in the branch shadow mode, comparing the guard indicator of the branch instructions with the guard indicator included in subsequent instructions and continuing to supply instructions if the guard indicators match, and preventing the supply of instructions if the guard indicators do not match; and disabling the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator. ### Claim 11 (depends on 10) A method according to claim 10, in which there is more than one execution unit and wherein normal instructions are supplied to a first execution unit, and branch instructions are supplied to a second execution unit. ### Claim 12 (depends on 11) A method according to claim 11, wherein the first set of execution units hold a master guard value store containing a master representation of current values for the guard indicators, the method comprising transferring the value of a guard indicator to the second set of execution units in order to resolve the branch. ### Claim 13 A computer system for executing instructions predicated on guard indicators included in the instructions, the instructions including normal instructions which are executed if the guard indicator is true and branch instructions which are executed if the guard indicator is false, the computer system comprising: instruction supply circuitry; at least one execution unit for receiving instructions from the supply circuitry: branch detection circuitry for detecting a branch instruction, for holding the guard indicator of the branch instruction and for setting a branch shadow mode; a comparer operable in the branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match; and a disabler for disabling the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator. ### Claim 14 (depends on 13) A computer system according to claim 13, which comprises a decoder for decoding the instructions and wherein the branch detection circuitry is located in the decoder. ### Claim 15 (depends on 13) A computer system according to claim 13, which comprises a plurality of parallel execution units for receiving respective said instructions from the instruction supply circuitry, wherein each instruction has a respective guard indicator selected from a set of guard indicators. ### Claim 16 (depends on 15) A computer system according two claim 15, wherein one of said execution units includes a master guard value store containing a master representation of current values for the guard indicators in said set of guard indicators, and another one of said execution units is responsible for executing branch instructions, said other execution unit being operable to request and receive from said master store a guard value for resolving a branch instruction. ### Claim 17 (depends on 13) A computer system according to claim 13, wherein the execution units include execution pipelines providing access to a data memory, said pipelines including a first set of pipelines for use in executed instructions need for memory access operations, a second set of pipelines arranged to carry out arithmetic operations, thereby providing decoupling of memory access operations from arithmetic operations, and a third pipeline for executing branch instructions. ### Claim 18 (depends on 17) A computer system according to claim 17, wherein the second set of pipelines and the third pipeline share an instruction queue holding instructions awaiting access to the pipelines, the third pipeline having a dedicated slot for holding branch instructions awaiting resolution while instructions from the instruction queue continue to be supplied to the pipelines. ### Claim 19 (depends on 13) A computer system according to claim 13, wherein the instruction supply circuitry comprises a control unit which includes a fetch branch address unit for holding a branch target address. ### Claim 20 (depends on 13) A computer system according to claim 13, in which the or each execution unit comprises a plurality of pipelined stages, with synchronized pipeline cycles for each of the execution units when a plurality of execution units are present. ### Claim 21 (depends on 1) A computer system according to claim 1, which comprises a plurality of pipelined stages for supplying, decoding and executing instructions.