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US 6,725,360 B1Granted
Selectively processing different size data in multiplier and ALU paths in parallel
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsBradley C. Aldrich, Jose Fridman, Paul Meyer, Gang Liang
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Abstract
An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.
Claims10
An integrated circuit comprising:
- a first processing path which processes data up to n-bits in an n-bit multiplier;
- a second processing path operating in parallel with said first path, including a plurality of arithmetic logic units which processes different data than the data in said first processing path up to (n/2)-bits in parallel with said first processing path;
- and
- a first multiplexer which controls providing of n bit data to said n bit multiplier, and a second multiplexer separate from said first processing path which controls providing n/2 bit data to said second processing path.
1 more element
A method of processing data comprising:
- determining a size of the data to be processed;
- and
- selecting a first processing path with an n-bit multiplier if the data size is greater than a first size;
- selecting a second processing path with arithmetic logic units if the data size is less than the first size;
- and
- operating said first and second processing paths in parallel.
3 more elements
Dependencies are inferred from the claim text.