Arithmetic processing architecture having a portion of general-purpose registers directly coupled to a plurality of memory banks

A microprocessor, comprising:

• an internal memory having a plurality of internal memory banks, an instruction memory, a plurality of general-purpose registers, an instruction fetch unit, a decoder, and an arithmetic logic unit,
• said plurality of internal memory banks storing operand data;
• said instruction memory storing a plurality of program instructions,
• said instruction fetch unit fetching a program instruction of said plurality of program instructions from said instruction memory;
• a first data register of said plurality of general-purpose registers for directly receiving said operand data from one of said internal memory banks;
• a second data register of said plurality of general-purpose registers for directly receiving presenting processed data to another one of said internal memory banks;
• a general-purpose register of said plurality of general-purpose registers receiving one of said operand data and said processed data;
• said decoder decoding said fetched program instruction and transferring said operand data from said general-purpose register to said arithmetic logic unit during a decoding cycle,
• said arithmetic logic unit producing said processed data by using said program instruction to perform at least one of an arithmetic operation and a logic operation,
• said processed data being transferred to said general-purpose register while simultaneously reading another program instruction of said plurality of program instructions from said instruction memory,
• wherein, said arithmetic logic unit produces and transfers said processed data within one clock cycle, said received operand data and received said processed data being transferable within said one clock cycle to an input of said arithmetic logic unit and to any of said plurality of general-purpose registers.