# US 6,725,354 B1 · Shared execution unit in a dual core processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,725,354 B1 - Document ID: US6725354B1 - Status: Granted - Kind: B1 - Application number: 09/594,631 - Filed: 2000-06-15 - Granted: 2004-04-20 - Earliest claimed: 2000-06-15 - Assignees: International Business Machines Corporation - Inventors: James Allan Kahle; Charles Roberts Moore - Web page: https://patentgrep.com/patent/US6725354B1 ## CPC - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/384: {Register renaming} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory} - G06F 9/3879: {for non-native instruction execution, e.g. executing a command; for Java instruction set} - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 15/7832: {on one IC chip (single chip microprocessors)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions. ## Claims ### Claim 1 A processor, comprising; first and second processor cores, each core including an execution unit suitable for processing data if the data is of a first type; means for distinguishing between data of the first type and data of a second type; a shared execution unit suitable for processing data of the second type wherein the shared execution unit includes a pair of matching execution pipes; and means for forwarding data of the second type to the shared execution unit. ### Claim 2 (depends on 1) The processor of claim 1, wherein data of the first type comprises an instruction selected from the group including fixed point instructions, load/store instructions, and branch instructions. ### Claim 3 (depends on 1) The processor of claim 1, wherein data of the second type comprises a floating point instruction. ### Claim 4 (depends on 1) The processor of claim 1, further comprising an arbiter connected to the shared execution unit for arbitrating between the first processor core and the second processor core for access to the shared execution unit. ### Claim 5 (depends on 4) The processor of claim 4, wherein each of the processor cores includes a shared execution enable bit, and wherein the arbiter arbitrates between the first and second cores based upon the state of the shared execution enable bits. ### Claim 6 (depends on 1) The processor of claim 1, wherein the shared execution unit is connected to and receives instructions from a shared issue unit. ### Claim 7 A method of operating a processor, comprising: executing a first instruction in an execution unit of a first core of a dual core processor if the first instruction is of a first type; executing a second instruction in an execution unit of a second core of the dual core processor if the second instruction is of the first type; and executing the first and second instructions in matching execution pipelines within a shared execution unit of the dual core processor if the instructions are of a second type. ### Claim 8 (depends on 7) The method of claim 7, wherein instructions of the first type comprises fixed point instructions, load/store instructions, and branch instructions. ### Claim 9 (depends on 7) The method of claim 7, wherein instructions of the second type comprise floating point instructions. ### Claim 10 (depends on 7) The method of claim 7, further comprising arbitrating between the first and second instructions for access to the shared execution unit if the instructions are of the second type. ### Claim 11 (depends on 10) The method of claim 10, wherein arbitrating between the first and second instructions includes determining the state of first and second floating point enables of the first and second cores respectively. ### Claim 12 (depends on 7) The method of claim 7, further comprising dispatching first and second instructions of the second type to a shared issue queue connected to the shared execution unit. ### Claim 13 A data processing system including system memory, hard disk, keyboard, mouse, and display, the system comprising: first and second processor cores, each core including an execution unit suitable for processing data if the data is of a first type; means for distinguishing between data of the first type and data of a second type; a shared execution unit suitable for processing data of the second type wherein the shared execution unit includes a matching pair of execution pipes; and means for forwarding data of the second type to the shared execution unit. ### Claim 14 (depends on 13) The system of claim 13, wherein the first type of data comprises an instruction selected from the group including fixed point instructions, load/store instructions, and branch instructions. ### Claim 15 (depends on 13) The system of claim 13, wherein the second type of data comprises a floating point instruction. ### Claim 16 (depends on 13) The system of claim 13, further comprising an arbiter connected to the shared execution unit for arbitrating between the first processor core and the second processor core for access to the shared execution unit. ### Claim 17 (depends on 16) The system of claim 16, wherein each of the processor cores includes a shared execution enable bit, and wherein the arbiter arbitrates between the first and second cores based upon the state of the shared execution enable bits. ### Claim 18 (depends on 13) The system of claim 13, wherein the shared execution unit is connected to and receives instructions from a shared issue unit.