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US 6,725,347 B2Granted
Spin-wheel SDRAM access scheduler for high performance microprocessors
AssigneeSun Microsystems, Inc.
InventorsLiuxi Yang, Duong Tong
Life of this patent
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Abstract
A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.
Claims13
An apparatus for controlling a memory device comprising:
- a command spin wheel that schedules a read or a write command for the memory device, wherein the command spin wheel forms a plurality of first-in, first-out queues and comprises a plurality of pointers;
- a read spin wheel that ensures correct timing of the read command, wherein the read spin wheel forms a first-in, first-out queue and comprises a plurality of pointers;
- and
- a write spin wheel that ensures correct timing of the write command, wherein the write spin wheel forms a first-in, first-out queue and comprises a plurality of pointers.
1 more element
An on-chip memory control unit for an SDRAM that serves a plurality of microprocessors, comprising:
- a command spin wheel that schedules read and write commands on a SDRAM command bus in a first-in, first-out order, the command spin wheel comprising,
- an auto-incremental release pointer,
- an auto-incremental CAS pointer, and
- an auto-incremental schedule pointer;
- a read spin wheel that ensures a proper timing sequence of a read command in a first-in, first-out order, the read spin wheel comprising,
- a data read request pointer, and
- a schedule pointer;
- and
- a write spin wheel that ensures a proper timing sequence of a write command in a first-in, first-out order, the write spin wheel comprising,
- a data push request pointer, and
- a schedule pointer.
8 more elements
An apparatus for controlling a memory device comprising:
- means for scheduling a read command or a write command for the memory device, wherein the means for scheduling forms a plurality of first-in, first-out Queues and comprises a plurality of pointers;
- means for ensuring a proper timing sequence for the read command, wherein the means for ensuring a proper timing secuence for the read command forms a first-in, first-out queue and comprises a plurality of pointers;
- and
- means for ensuring a proper timing sequence for the write command, wherein the means for ensuring a proper timing sequence for the write command forms a first-in, first-out queue and comprises a plurality of pointers.
1 more element
A method for controlling a memory device comprising:
- scheduling a read or a write command for the memory device, wherein the command spin wheel forms a plurality of first-in, first-out queues and comprises a plurality of pointers;
- ensuring a proper timing sequence for a read command, wherein the read spin wheel forms a first-in, first-out queue and comprises a plurality of pointers;
- and
- ensuring a proper timing sequence for a write command, wherein the write spin wheel forms a first-in, first-out queue and comprises a plurality of pointers.
1 more element
Dependencies are inferred from the claim text.