Mechanism for folding storage barrier operations in a multiprocessor system

A data processing system comprising:

• a processor coupled to an interconnect;
• a memory;
• an instruction sequence that includes a first barrier instruction and a second barrier instruction that is separated from the first barrier instruction by a store instruction;
• and
• means for issuing to said interconnect a store request associated with said store instruction out of sequence with respect to a first barrier operation of said first barrier instruction, whereby said store request is issued prior to the first barrier operation;
• means for determining when said store request completes before said first barrier operation is issued;
• and
• means, responsive to said determination, for issuing only a single barrier operation corresponding to the second barrier instruction in lieu of issuing separate barrier operations for both said first and second barrier instructions.

A processor comprising:

• an instruction sequencing unit (ISU);
• a load store unit (LSU) which receives an instruction sequence from said ISU, said instruction sequence including a first barrier instruction and a second barrier instruction and at least one store instruction sequentially between said first barrier instruction and second barrier instructions in said instruction sequence;
• and
• a controller, which issues to an interconnect a store requests a associated with said store instruction out of sequence with respect to a first barrier operation associated with said first barrier instruction, whereby said store request is issued prior to the first barrier operation;
• means for determining when said store request completes before said first barrier operation is issued;
• and
• means, responsive to said determination, for issuing only a single barrier operation corresponding to the second barrier instruction in lieu of issuing separate barrier operations for both said first and second barrier instructions.