Method and apparatus for combining architectures with logic option

A logic circuit for outputting data from a memory device using one of a plurality of data bus width configurations, comprising:

• a plurality of I/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths;
• a level translator provided in a data path of said I/O circuits;
• and
• a circuit for selectively operating said first and second I/O circuits in said first and second bus width configurations such that in said first bus width configuration said first I/O circuit outputs data from said first memory array and said second I/O circuit outputs data from said second memory array, and in said second bus width configuration said first I/O circuit does not output data and said second I/O circuit outputs data from said first and second memory arrays.

A memory system including a memory device having a settable bus width configuration, said memory device comprising:

• a plurality of I/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths;
• a level translator provided in a data path of said I/O circuits;
• and
• a circuit for selectively operating said first and second I/O circuits in said first and second bus width configurations such that in said first bus width configuration said first I/O circuit outputs data from said first memory array and said second I/O circuit outputs data from said second memory array, and in said second bus width configuration said first I/O circuit does not output data and said second I/O circuit outputs data from said first and second memory arrays.

A processor system, comprising:

• a processor;
• and
• a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising:
• a steering logic circuit for selectively outputting data from a plurality of memory arrays in at least one of first and second bus width configurations, wherein said data passes through said steering logic circuit when going from at least one of said plurality of memory arrays to at least one sense amplifier circuit;
• and
• a level translator provided between a memory array and said at least one sense amplifier circuit.

A processor system, comprising:

• a processor;
• and
• a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising:
• a plurality of I/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths;
• a level translator provided in a data path of said I/O circuits;
• and
• a circuit for selectively operating said first and second I/O circuits in said first and second bus width configurations such that in said first bus width configuration said first I/O circuit outputs data from said first memory array and said second I/O circuit outputs data from said second memory array, and in said second bus width configuration said first I/O circuit does not output data and said second I/O circuit outputs data from said first and second memory arrays.

A method of operating a memory device with a plurality of data bus width configurations, comprising:

• providing a differential input signal to at least one sense amplifier circuit, said at least one sense amplifier outputting differential data on an output data path;
• outputting data from a first memory array through a first I/O circuit and from a second memory array through a second I/O circuit when a first bus width configuration is selected;
• outputting data from a selected one of said first memory array and said second memory array through said second I/O circuit when a second bus width configuration is selected;
• and
• setting said second I/O circuit to use one of said first and second data bus width configurations according to a control signal.

A memory system including a memory device having a settable width configuration, said memory device comprising:

• a first and second I/O circuit, each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a first and second data bus width configurations;
• a circuit for selectively operating said first and second I/O circuits in said first and second bus width configurations such that in said first bus width configuration said first I/O circuit outputs data from said first memory array and said second I/O circuit outputs data from said second memory array, and in said second bus width configuration said first I/O circuit does not output data and said second I/O circuit successively outputs data from said first and second memory arrays;
• and
• a switching element for selectively operating of said first and second I/O circuits in said first and second bus width configurations in response to a selection value received on an address input data path;
• wherein first and second I/O circuits are interconnected such that in said second bus width configuration data from said first memory array passes through said first I/O circuit to said second I/O circuit.

A processor system comprising:

• a processor;
• and
• a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising:
• a first and second I/O circuit, each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a first and second data bus width configurations;
• a circuit for selectively operating said first and second I/O circuits in said first and second bus width configurations such that in said first bus width configuration said first I/O circuit outputs data from said first memory array and said second I/O circuit outputs data from said second memory array, and in said second bus width configuration said first I/O circuit does not output data and said second I/O circuit successively outputs data from said first and second memory arrays;
• and
• a switching element for selectively operating of said first and second I/O circuits in said first and second bus width configurations in response to a selection value received on an address input data path;
• wherein first and second I/O circuits are interconnected such that in said second bus width configuration data from said first memory array passes through said first I/O circuit to said second I/O circuit.