Multi-bank memory subsystem employing an arrangement of multiple memory modules

A memory subsystem comprising:

• a memory controller unit;
• a memory bus coupled to said memory controller unit, wherein said memory bus includes a plurality of data paths each formed by a separate grouping of data lines;
• a first plurality of memory modules coupled to said memory bus that provide storage corresponding to a first memory bank, wherein said first memory bank is configured to store data corresponding to a first range of addresses;
• and
• a second plurality of memory modules coupled to said memory bus that provide storage corresponding to a second memory bank, wherein said second memory bank is configured to store data corresponding to a second range of addresses;
• wherein a separate memory module of each of said first and said second memory banks is coupled to each data path of said memory bus;
• and
• wherein memory modules that are coupled to the same data path of said memory bus are located adjacent to one another without intervening memory modules coupled to other data paths.

A data processing system comprising:

• a processor;
• a memory controller unit coupled to said processor;
• a memory bus coupled to said memory controller unit, wherein said memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines associated with said memory;
• a first memory module and a second memory module coupled to said memory bus that provide storage corresponding to a first memory bank, wherein said first memory bank is configured to store data corresponding to a first range of addresses;
• and
• a third memory module and a fourth memory module coupled to said memory bus that provide storage corresponding to a second memory bank, wherein said second memory bank is configured to store data corresponding to a second range of addresses;
• wherein said first memory module and said third memory module are coupled to a first data path of said memory bus and said second memory module and said fourth memory module are coupled a second data path of said memory bus;
• and
• wherein said first and said third memory modules are located adjacent to one another and said second and said fourth memory modules are located adjacent to one another without intervening memory modules coupled to other data paths.