Multistage interrupt controller for receiving a plurality of interrupt signals to generate a priority interrupt signal
AssigneeHyundai Electronics Industries Co., Ltd.
InventorBong Kyun Kim
Life of this patent
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Abstract
A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive and provide temporary storage for corresponding external interrupt signals, an interrupt priority determining circuit that can receive the external interrupt signals from the multistage interrupt reception registers, determine priorities of the external interrupt signals, and dispose of the external interrupt signals according to the priorities, and a logical operator that inverts signals generated by the corresponding multistage interrupt reception registers and provides a logical feedback signal to the multistage interrupt reception registers.
Claims15
A multistage interrupt controller, comprising:
- a plurality of multistage interrupt reception registers, each receiving and storing a plurality of interrupt signals to generate a priority interrupt signal;
- an interrupt priority determining circuit coupled to said plurality of multistage interrupt reception registers for receiving corresponding priority interrupt signals, determining priorities of the priority interrupt signals, and generating an output signal in accordance with the priorities;
- a feedback circuit that receives the priority interrupts signals from the multistage interrupt reception registers to generate a feedback signal to each of the plurality of multistage interrupt reception registers, wherein:
- each of the plurality of multistage interrupt reception registers comprises a plurality of stages coupled in series, wherein each of the stages receives the feedback signal and at least one of the interrupt signal and at least one delayed interrupt signal;
- and
- a first stage of the plurality of stages comprises:
- a first logic gate that receives the feedback signal, and at least one delayed interrupt signal and performs a logic operation to generate a first logic gate output;
- a second logic gate that performs a logic operation on the first logic gate output and a synchronization signal to generate a second logic gate output;
- and
- a flip-flop that receives a corresponding interrupt signal to generate the delayed interrupt signal in response to the second logic gate output.
A multistage interrupt controller comprising:
- a plurality of stages coupled in series, wherein each stage receives a feedback signal and at least one of an interrupt signal and at least one delayed interrupt signal and a last stage of the plurality of stages generates a priority interrupt signal;
- a feedback circuit responsive to the priority interrupt signal to generate the feedback signal, wherein a first stage of the plurality of stages comprises:
- a first logic gate that performs a logic operation based on the at least one delayed interrupt signal and the feedback signal to generate a first logic gate output;
- a second logic gate that performs a logic operation based on the first logic gate output and a synchronization signal to generate a second logic gate output;
- and
- a flip-flop that receives a corresponding interrupt signal to generate the delayed interrupt signal in response to the second logic gate output.
Dependencies are inferred from the claim text.