Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system

A data processing system comprising:

• a plurality of master devices;
• a plurality of bidirectional master device buses, wherein a master device bus connects one or more master devices to a bus access controller;
• a bus access controller (BAC) including:
• an address BAC (ABAC), wherein the DBAC is connected to each master device bus in the plurality of master device buses;
• a data BAC (DBAC), wherein the DBAC is connected to each master device bus in the plurality of master device buses;
• a set of control lines between the ABAC and the DBAC;
• and control means for generating and sending data flow commands from the ABAC to the DBAC, wherein the commands are multibeat data transactions.

A bus access controller (BAC) comprising:

• an address BAC (ABAC), wherein the ABAC is connectable to a plurality of master device buses;
• a data BAC (DBAC), wherein the DBAC is connectable to a plurality of master device buses;
• a set of control lines between the ABAC and the DBAC;
• a plurality of ABAC ports, wherein each DBAC port connects to address/control lines of each master device bus;
• and
• a plurality of DBAC ports, wherein each DBAC port connects to data lines of each mater device bus.

A bus access controller (BAC) comprising:

• an address BAC (ABAC), wherein the DBAC is connectable to a plurality of master device buses;
• a data BAC (DBAC), wherein the DBAC is connectable to a plurality of master device buses;
• a set of control lines between the ABAC and the DBAC;
• and
• control means for generating and sending data flow commands from the ABAC to the DBAC, wherein the commands are multibeat data transactions.

A bus control device comprising:

• a set of one or more node data controllers, wherein each of the node data controllers provides a portion of a data path between a memory subsystem and a master device;
• a node address controller;
• and
• a command interface between the set of node data controllers and the node address controller, wherein the node address controller comprises:
• a plurality of master device address ports, wherein each master device address port connects to an address/control portion of a master device bus;
• a pair of address switch ports, wherein each address switch port connects to one of a pair of unidirectional address switch buses, wherein one of the pair of address switch buses conveys an address from the bus control device to the address switch and one of the pair of address switch buses conveys an address from the address switch to the bus control device;
• and
• a set of control queues, wherein the control queues support transfer of data through data queues in the node data controller.