System solution to allow 64-bit PCI adapters to determine state during reset
AssigneeInternational Business Machines Corporation
InventorsGhadir Robert Gholami, Mark David McLaughlin, John Daniel Upton
Life of this patent
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Abstract
A modified system causes the REQ64# signal to be asserted when the adapter is in reset on a 64-bit slot. This allows the adapter to see that it is in a 64-bit slot at the beginning of reset, preventing the adapter from driving the 64-bit extension pins. The above-described modification must be made to all the 64-bit slots on a system. When the reset signal is active, it will cause the buffer to drive the REQ64# signal low. This will synchronize reset and REQ64#, eliminating the possibility for bus contention. No modification is necessary for 32-bit slots. This modification will not affect the normal operation of the bus, since it is only used during reset.
Claims15
A method in a data processing system for allowing an adapter to determine data width, comprising:
- receiving a reset signal on a reset signal line from a system host bridge;
- synchronizinig a data width signal with the reset signal, wherein the data width signal on a data width signal line is asserted immediately in response to the reset signal being asserted;
- wherein the data width signal line is connected between the system host bridge and at least one adapter bridge located in at least one adapter slot;
- and
- wherein the data width signal, when asserted, indicates at the beginning of reset that the adapter slot is a 64-bit adapter slot.
A method in a data processing system for allowing an adapter to determine data width, comprising;
- receiving a reset signal;
- synchronizing a data width signal with the rest signal, wherein the data width signal is asserted immediately in response to the reset signal being asserted;
- wherein the data width signal is asserted on a data width signal line connected between a system host bridge and at least one adapter bridge located in at least one adapter slot;
- and
- wherein the data width signal, when asserted, indicates at the beginning of reset that the adapter slot is a 64-bit adapter slot.
An apparatus comprising;
- a system host bridge providing a reset signal line for providing a reset signal, and a data width signal line for providing a data width signal;
- at least one adapter bridge, located in at least one adapter slot, connected to the data width signal line;
- and
- a tri-state buffer having an input connected to ground, an output connected to the data width signal line, and an enable pin connected to the rest signal line;
- wherein, when reset is asserted, the output of the tri-state buffer follows the input and the data width signal is asserted and, when reset is deasserted, the data width signal is driven by the system host bridge or the at least one adapter bridge;
- said data width signal being synchronized with said reset signal, wherein said data width signal is asserted immediately in response to said reset signal being asserted;
- and
- wherein said data width signal, when asserted, indicates at the beginning of reset that said adapter slot is a 64-bit adapter slot.
An apparatus comprising;
- a system host bridge providing a reset signal using a reset signal line and providing a data width signal using a data signal line;
- at least one adapter bridge, located in at least one adapter slot, connected to the data width signal line;
- a tri-state buffer having an input connected to a low-level signal source, an output connected to the data width signal line, and an enable pin connected to the reset signal line,
- said data width signal being synchronized with said reset signal, wherein said data width signal is asserted immediately in response to said reset signal being asserted;
- and
- wherein said data width signal, when asserted, indicates at the beginning of reset that said adapter slot is a 64-bit adapter slot.
An apparatus for allowing an adapter to determine data width, comprising;
- means for receiving a reset signal;
- means for asserting the data width signal in response to the reset signal being asserted;
- said data width signal being synchronized with said reset signal, wherein said data width signal is asserted immediately in response to said reset signal being asserted;
- wherein the data width signal is asserted on a data width signal line connected between a system host bridge and at least one adapter bridge located in at least one adapter slot;
- and
- wherein the data width signal, when asserted, indicates at the beginning of reset that the adapter slot is a 64-bit adapter slot.
Dependencies are inferred from the claim text.