FIFO overflow management
AssigneeCanon Kabushiki Kaisha
InventorKok Tjoan Lie
Life of this patent
Estimating the term…
Abstract
Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.
Claims9
A method of improving the performance of a pipeline system in which a FIFO is incorporated in said pipeline between an upstream processing module and a downstream processing module, each of said modules having access to a common external memory, said method being characterised by:
- said upstream module detecting when said FIFO is substantially full and outputting a first special command to said FIFO indicating that commands output following the special command are to be sourced from said external memory, said upstream module thereafter transferring said following commands from said upstream module to said external memory;
- and
- said downstream module interpreting commands from each of said FIFO and said external memory to determine a source of said commands wherein upon receipt of said first special command from said FIFO, said downstream module sources said following commands from said external memory.
A pipelined processor system comprising:
- an upstream processor module;
- a downstream processor module;
- a FIFO arrangement coupling an output of said upstream module to an input of said downstream module to thus form a processor pipeline;
- a memory module accessible by each of said processor modules;
- said upstream module having an overload arrangement configured to detect a filling of said FIFO arrangement by commands output from said upstream module and to thereby output a special command to said FIFO arrangement indicating that commands output following said special command are to be sourced from said memory module, and to thereafter direct said following commands output from said upstream module for intermediate storage in said memory module;
- and
- said downstream module having an interpreting arrangement configured to interpret commands received from each of said FIFO arrangement and said memory module to determine a source of said commands to be input to said downstream module, a receipt of said special command from said FIFO directing said downstream module to source said commands from said memory module.
An integrated circuit processor device comprising:
- a processor pipeline including at least an upstream module, a downstream module and a FIFO arrangement, said FIFO arrangement being configured to couple an ordered sequence of commands output from said upstream module to an input of said downstream module;
- a memory module independently accessible by each of said upstream and downstream modules;
- an overload arrangement forming part of said upstream module and configured to detect a filling of said FIFO arrangement by said commands output from said upstream module and to thereby output a first special command to said FIFO arrangement indicating that commands output following said special command are to be sourced from said memory module, and to thereafter direct said following commands output from said upstream module for intermediate storage in said memory module, said overload arrangement being further configured to generate a second special command in response to said FIFO arrangement having a predetermined number of available locations, said second special command being output to said memory module and thereafter to direct subsequent ones of said commands output from said upstream module to said FIFO arrangement;
- and
- an interpreting arrangement forming part of said downstream module and configured to interpret commands received from each of said FIFO arrangement and said memory module to determine a source of said commands to be input to said downstream module, a receipt of said first special command from said FIFO arrangement directing said downstream module to source said commands from said memory module and a receipt of said second special command from said memory module directing said downstream module to source said subsequent commands from said FIFO arrangement.
Dependencies are inferred from the claim text.