Decimation filter and signal processing method using the same
AssigneesHitachi, Ltd., International Superconductivity Technology Center, NEC Corporation, Kabushiki Kaisha Toshiba
InventorsHaruhiro Hasegawa, Kazunori Miyahara, Tatsunori Hashimoto, Shuichi Nagasawa, Youichi Enomoto
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Abstract
A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.
Claims16
A decimation filter, comprising:
- delay units for sequentially delaying an input signal one clock and for producing a plurality of delayed signals;
- adders for sequentially adding the delayed signals to each other and for producing total signals;
- and
- a counter connected to outputs from said adders for counting pulses of the total signals from said adders.
A signal processing method for use with a decimation filter, comprising the steps of:
- sequentially delaying an input signal one clock and for producing a plurality of delayed signals;
- sequentially adding with adders the delayed signals to each other and for producing total signals;
- and
- counting pulses of the total signals from said adders.
A decimation filter, comprising:
- a first block for sequentially delaying an input signal one clock and for producing a plurality of delayed signals;
- adders for sequentially adding the delayed signals to each other and for producing total signals;
- and
- a second block connected to outputs of said adders for counting pulses of the total signals from said adders.
Dependencies are inferred from the claim text.