High speed programmable counter architecture
AssigneePC Peripherals Inc.
InventorNicholas J. Bucska
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Abstract
A high speed programmable counter architecture is disclosed. In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler and an m bit low speed counter. An input signal can be divided by any value equal to or greater than j*2n. The modulus of division can be provided to the programmable counter in binary form directly, without requiring complex calculations or decoding circuitry. The present invention allows high speed programmable counters to be provided that are capable of dividing by much smaller numbers than conventional counters, including numbers less than 2n*(2n−1), wherein n is equal to the number of bits in a high speed prescaler.
Claims17
A programmable composite counter, comprising:
- a multiple bit data bus, wherein said data bus carries a signal comprising m most significant bits and n least significant bits of an m+n bit modulus;
- an n-bit programmable high speed prescaler, comprising:
- a clock signal input;
- a trigger signal input;
- n prescaler inputs interconnected to said n least significant bits of said multiple bit data bus;
- a low frequency output;
- an m-bit programmable low speed counter, comprising:
- a signal input, wherein said signal input is interconnected to said low frequency output of said high speed prescaler;
- m start value inputs interconnected to said m most significant bits of said multiple bit data bus;
- and
- an output, wherein a frequency of an output signal from said output of said programmable low speed counter is equal to a frequency of a signal provided to said clock signal input of said high speed prescaler divided by said modulus, wherein a minimum value of said modulus is 2n.
A method of frequency dividing a clock signal, comprising:
- providing a count modulus;
- providing an m bit low speed counter;
- providing a clock signal to be divided by said count modulus;
- providing m most significant bits of said count modulus to said m bit low speed counter;
- providing a programmable n bit high speed prescaler;
- providing n least significant bits of said count modulus to said high speed prescaler;
- providing an output of said high speed prescaler as an input to said low speed counter;
- and
- interconnecting a carry bit output of said low speed counter to said high speed prescaler, wherein activating said carry bit output of said low speed counter extends a cycle of said high speed counter from 2n to 2n+N, where N is a value encoded by the n least significant bits of said count modulus.
A method of frequency dividing an input signal, comprising:
- receiving a modulus to divide by, wherein said modulus to divide by is encoded by m+n bits;
- receiving an input signal;
- and
- generating an output signal, wherein said output signal has a frequency equal to a frequency of said input signal divided by said modulus, wherein said modulus has any value within a range from 2n to 2m+n.
A frequency divider, comprising:
- a multiple bit data bus for carrying a signal representing a modulus of said frequency divider, wherein said multiple bit data bus comprises n+m bits;
- an n-bit prescaler comprising at least n inputs interconnected to said multiple bit data bus to receive n bits from said multiple bit data bus, wherein an output cycle of said prescaler can be selectively extended by from 0 to 2n−1 counts according to a value represented by said n bits.
Dependencies are inferred from the claim text.