# US 6,725,187 B1 · Latch inference using dataflow analysis

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- Number: US 6,725,187 B1
- Document ID: US6725187B1
- Status: Granted
- Kind: B1
- Application number: 09/592,125
- Filed: 2000-06-12
- Granted: 2004-04-20
- Earliest claimed: 1998-12-16
- Assignees: Cadence Design Systems, Inc.
- Inventors: Szu-Tsung Cheng; Alexander Saldanha; Patrick C. McGeer; Patrick Scaglia
- Web page: https://patentgrep.com/patent/US6725187B1

## CPC

- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

## Claims

### Claim 1

A method of determining whether a latch is represented in an expression of a circuit using data flow analysis, the method comprising the steps of:
identifying a set of variables Lp used in the expression;
for a variable within the set Lp, conducting an uninitialized variable analysis for a given input signal;
if the variable is accessed while uninitialized, inferring a latch for that variable.

### Claim 2 (depends on 1)

The method of claim 1, further comprising the step of inferring a wire if an uninitialized variable is not accessed.

### Claim 3 (depends on 1)

The method of claim 1, further comprising the step of determining the conditions under which the variable is modified, and from the conditions inferring a clocking signal for the inferred latch.

### Claim 4

A system for determining whether a latch is represented in an expression of a circuit using data flow analysis, the system comprising:
means for identifying a set of variables Lp used in the expression;
means for conducting, for a variable within the set Lp, an uninitialized variable analysis for a given input signal; and
means for inferring, if the variable is accessed while uninitialized, a latch for that variable.

### Claim 5 (depends on 4)

The system of claim 4, further comprising means for inferring a wire if an uninitialized variable is not accessed.

### Claim 6 (depends on 4)

The system of claim 4, further comprising means for determining the conditions under which the variable is modified, and from the determined conditions inferring a clocking signal for the latch.

### Claim 7

A method of inferring latch elements from an HDL file using data flow analysis; the method comprising the step of:
inferring a latch if an accessed variable in an HDL expression is uninitialized for a given input signal.

### Claim 8 (depends on 7)

The method of claim 7 further comprising the step of:
inferring a wire if the uninitialized variable is not accessed.

### Claim 9

A method for selectively inferring latch elements in a circuit design from an HDL file; the method comprising the steps of:
modeling the file as a plurality of data flow equations;
analyzing said equations for uninitialized variables; and
placing a latch at each utilized unitialized variable.