Method of logic simulation
AssigneeWinbond Electronics Corp.
InventorShang-Tzu Ju
Life of this patent
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Abstract
The present invention is related to a method of logic simulation performed by a simulator for solving the problem of the false unknown state. The method includes steps of defining a high potential state, a low potential state, an unknown state and an inverse unknown state for a plurality of nodes of a logic circuit, obtaining a plurality of truth tables according to the high potential state, the low potential state, the unknown state and the inverse unknown state, and achieving the logic simulation according to the plural truth tables.
Claims34
A method of logic simulation, comprising steps of:
- (1) defining a high potential state, a low potential state, an unknown state and a fourth state for a plurality of nodes of a logic circuit;
- (2) obtaining a simulating reference according to said high potential state, said low potential state, said unknown state and said fourth state;
- and
- (3) achieving said logic simulation according to said simulating reference.
A simulating reference of a NAND gate, adapted to be used in logic simulation, obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of said NAND gate.
A simulating reference of a NOR gate, adapted to be used in logic simulation, obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of said NOR gate.
A simulating reference of a NOT (INV) gate, adapted to be used in logic simulation, obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for an input node and an output node of said NOT (INV) gate.
Dependencies are inferred from the claim text.