# US 6,724,851 B2 · FIR chip for use in a wireless subscriber unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,851 B2 - Document ID: US6724851B2 - Status: Granted - Kind: B2 - Application number: 10/412,456 - Filed: 2003-04-11 - Published: 2003-10-09 - Granted: 2004-04-20 - Earliest claimed: 1989-08-14 - Inventors: David Norton Critchlow; Moshe Yehushua; Graham Martin Avis; Wade Lyle Heimbigner; Karle Joseph Johnson; George Alan Wiley - Web page: https://patentgrep.com/patent/US6724851B2 ## CPC - H04L 25/03343: {Arrangements at the transmitter end} - H03D 3/007: {by converting the oscillations into two quadrature related signals (H03D3/245 takes precedence)} - H04L 27/00: Modulated-carrier systems - H04L 27/2092: {with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)} - H03B 28/00: Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations (analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in AC-AC converters H02M5/18) - H03C 3/00: Angle modulation (H03C5/00, H03C7/00 take precedence) - H04L 2025/03375: {Passband transmission} - H04L 2025/03477: {not time-recursive} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) - H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H) - H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M) ## Abstract A FIR chip is used in a wireless subscriber unit. The subscriber unit includes a processor for transcoding an input signal to provide digital input symbols. A received output signal is demodulated. Digital output symbols are synthesized from the demodulated output signal processor and filtered digital input symbols are provided. An internal address decoder decodes to allow the processor to access internal functions of the FIR chip. A control and status register allows the processor to read the status of and control the internal functions of the FIR chip. A FIR filter filters the digital input symbols. A transmit timer controls timing which allows the processor to control the FIR filter. A receive timer generates timing signals for timing transcoding operations and synthesizing operations connected to the processor. ## Claims ### Claim 1 A FIR chip for use in a wireless subscriber unit wherein the subscriber unit includes a processor for transcoding an input signal to provide digital input symbols for demodulating a received output signal, for synthesizing digital output symbols from the demodulated output signal processor and for providing filtered digital input symbols, the FIR chip comprising: an internal address decoder for internal address decoding to allow the processor to access internal functions of the FIR chip; a control and status register which allows the processor to read the status of and control the internal functions of the FIR chip; a FIR filter for FIR filtering the digital input symbols; a transmit timer for control timing which allows the processor to control the FIR filter; and a receive timer for generating timing signals for timing transcoding operations and synthesizing operations connected to the processor. ### Claim 2 (depends on 1) The FIR of claim 1 further including a ringer control operatively associated with the control and status register, said ringer control permitting the processor to control a ringer circuit of the subscriber unit. ### Claim 3 (depends on 2) The FIR chip of claim 2 further including a watchdog timer circuit operatively associated with the control and status register for resetting said processor. ### Claim 4 (depends on 1) The FIR chip of claim 1 further including a sample buffer having operative association with the processor and for buffering receive data samples before the data samples are output to the processor. ### Claim 5 (depends on 1) The FIR chip of claim 1 further including a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to a receiver timer. ### Claim 6 (depends on 1) The FIR chip of claim 1 further including an external address decoder for operative association with the processor to permit the processor to access the remaining components of the subscriber unit. ### Claim 7 A wireless subscriber unit includes a processor for transcoding an input signal to provide digital input symbols for demodulating a received output signal and from synthesizing digital output symbols for the demodulated output signal, the subscriber unit comprising a FIR chip including; an external address decoder means for internal address decoding connected to the processor, to allow the processor to access the internal functions of the FIR chip; a FIR filter for FIR filtering, connected to the processor to control the FIR filter; a transmit timer for control timing which allows the processor to control the FIR filter; a receive timer for generating timing signals for timing transcoding operations and synthesizing operations in the processor; a control and status register, connected to the processor, which allows the processor to read the status of and control the internal functions of an integrated circuit; a ringer control connected to the control and status register, said ringer control allows the processor to control a ringer circuit of the subscriber unit; a watchdog timer circuit, connected to the control and status register, for resetting said processor; a sample buffer for buffering received data samples before the data samples are output to the processor; a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to a CODEC timer; and an external address decoder, connected to the processor which allows the processor to access the remaining components of the subscriber unit.