# US 6,724,850 B1 · Deterministic hardware behavior between multiple asynchronous clock domains through the novel use of a PLL

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- Number: US 6,724,850 B1
- Document ID: US6724850B1
- Status: Granted
- Kind: B1
- Application number: 09/652,645
- Filed: 2000-08-31
- Granted: 2004-04-20
- Earliest claimed: 2000-08-31
- Assignees: Hewlett-Packard Development Company, L.P.
- Inventors: David Hartwell
- Web page: https://patentgrep.com/patent/US6724850B1

## CPC

- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H04L 7/0012: {by comparing receiver clock with transmitter clock}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.

## Claims

### Claim 1

An apparatus to pass data between a fast clock domain and a slow clock domain comprising:
a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
a first state machine to receive the first reference clock and a first divisor to generate a second reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock; and
a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.

### Claim 2 (depends on 1)

The apparatus as in claim 1, further comprising:
a third PLL circuit to receive the second clock from the second PLL circuit to generate a third clock in the slow domain; and
a latch circuit to receive the third clock and the slow to fast data transfer enable signal, wherein when the slow to fast transfer enable signal is enabled, the latch passes data from the slow to the fast clock domain.

### Claim 3 (depends on 1)

The apparatus as in claim 1, further comprising:
a latch circuit to receive the first clock and the fast to slow data transfer enable signal, wherein when the fast to slow transfer enable signal is enabled, the latch passes data from the fast to the slow clock domain.

### Claim 4 (depends on 1)

The apparatus as in claim 1, wherein the first state machine includes a counter to count to the received first divisor and on completion of the count, the counter generates the fast to slow transfer enable signal.

### Claim 5 (depends on 1)

The apparatus as in claim 1, wherein the second state machine includes a counter to count to the received second divisor and on completion of the count, the counter generates the slow to fast transfer enable signal.

### Claim 6

An apparatus to pass data between a fast clock domain and a slow clock domain comprising:
a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
means for receiving the first reference clock and a first divisor to generate a second reference clock and further generating a fast to slow data transfer enable signal based on the first divisor;
a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase relationship with the first clock; and
means for receiving the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.

### Claim 7

A computer system to pass data between a fast clock domain and a slow clock domain comprising:
a processing unit to transmit a forwarding clock;
an input/output (I/O) bridge that includes,
a first phase-locked loop (PLL) circuit to receive the forwarding clock and to generate a first clock for the fast clock domain;
a first state machine to receive the forwarding clock and a first divisor to generate a reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
a second PLL circuit to receive the reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock; and
a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.

### Claim 8 (depends on 7)

The system as in claim 7, wherein the I/O bridge further comprises:
a third PLL circuit to receive the second clock from the second PLL circuit to generate a third clock in the slow domain; and
a latch circuit to receive the third clock and the slow to fast data transfer enable signal, wherein when the slow to fast transfer enable signal is enabled, the latch passes data from the slow to the fast clock domain.

### Claim 9 (depends on 7)

The system as in claim 7, wherein the I/O bridge further comprises:
a latch circuit to receive the first clock and the fast to slow data transfer enable signal, wherein when the fast to slow transfer enable signal is enabled, the latch passes data from the fast to the slow clock domain.

### Claim 10 (depends on 7)

The system as in claim 7, wherein the first state machine includes a counter to count to the received first divisor and on completion of the count, the counter generates the fast to slow transfer enable signal.

### Claim 11 (depends on 7)

The system as in claim 7, wherein the first state machine includes a counter to count to the received first divisor and on completion of the count, the counter generates the fast to slow transfer enable signal.

### Claim 12

A method for passing data between a fast clock domain and a slow clock domain, the method comprising:
providing a first phase-locked loop (PLL) circuit to receive a first reference clock and to generate a first clock for the fast clock domain;
providing a first state machine to receive the first reference clock and a first divisor to generate a second reference clock, the first state machine further generates a fast to slow data transfer enable signal based on the first divisor;
providing a second PLL circuit to receive the second reference clock and to generate a second clock for the slow clock domain, the second clock placed in fixed phase and edge relationship with the first clock; and
providing a second state machine to receive the second clock and a second divisor to generate a feedback clock for the second PLL circuit and to generate a slow to fast data transfer enable signal based on the second divisor.

### Claim 13 (depends on 12)

The method as in claim 12, further comprising:
providing a third PLL circuit to receive the second clock from the second PLL circuit to generate a third clock in the slow domain; and
providing a latch circuit to receive the third clock and the slow to fast data transfer enable signal, wherein when the slow to fast transfer enable signal is enabled, the latch passes data from the slow to the fast clock domain.

### Claim 14 (depends on 12)

The method as in claim 12, further comprising:
providing a latch circuit to receive the first clock and the fast to slow data transfer enable signal, wherein when the fast to slow transfer enable signal is enabled, the latch passes data to the from the fast slow clock domain.