Simple, high performance, bit-sliced mesochronous synchronizer for a source synchronous link
AssigneeHewlett-Packard Development Company, L.P.
InventorKaren Lo
Life of this patent
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Abstract
The present invention provides a highly reliable synchronizer which provides excellent synchronization without using complicated PLL or DLL circuitry, which is simple to test, which is easily adaptable to systems which use bit-sliced data, and which does not require large chip area. The synchronizer is comprised of a first stage, a data capture circuit, preferably comprised of pair of master-slave flip-flops, that is electrically coupled to a second stage, a data selection circuit that preferably includes a FIFO comprised of N transparent latches that are electrically coupled to a multiplexer. The lack of complexity of the synchronizer design makes it smaller, faster, easier to test, and less prone to design error and manufacturing limits.
Claims21
A synchronizer for synchronizing data latched from a first clock domain to a second clock domain, comprised of:
- a data buffering circuit including a plurality of data latches for storing data from a sending chip, wherein the data from the sending chip is latched in the first clock domain;
- a read select circuit including a cycle delay storage element, the read select circuit electrically coupled to the data buffering circuit, wherein the read select circuit controls when data is read from the data buffering circuit into the second clock domain of the receiving chip, where data is read from the data buffering circuit a predetermined number of cycles after receiving a unique clock cycle identifier, wherein the predetermined number of cycles is determined by the a value of the cycle delay storage element.
A synchronizer for synchronizing data latched from a first clock domain to a second clock domain, comprised of:
- a data buffering circuit including a plurality of data latches for storing data from a sending chip, wherein each data latch is activated in turn according to a symbol shifted through a shift register in the first clock domain;
- and
- a read select circuit including a data selector having a plurality of inputs coupled to the data latches for selectively reading data from the latches in the second clock domain wherein the data selector is controlled to select each of the data latches in turn according to a delay of a predetermined number of clock cycles.
Dependencies are inferred from the claim text.