Threshold detector for detecting synchronization signals at correlator output during packet acquisition

A baseband processor for a radio frequency (RF) communication device, comprising:

• an analog to digital converter (ADC) that converts received analog baseband signals to digital baseband signals;
• decimation filters, coupled to the ADC, that coverts the digital baseband signals to digital samples at a selected sample rate;
• and
• a synchronization timing estimator, coupled to the decimation filters, comprising:
• a correlator that compares the digital samples from the decimation filters with predetermined synchronization signals and that provides digital correlation samples indicative thereof;
• a short-term integrator, coupled to the correlator, that integrates a first predetermined number of the digital correlation samples and that provides a short term moving average signal;
• a long-term integrator, coupled to the correlator, that integrates a second predetermined number of the digital correlation samples and that provides a long term moving average signal, the second predetermined number greater than the first predetermined number;
• a multiplier, coupled to the long-term integrator, that multiplies the long term moving average signal by a predetermined scale factor and that provides a corresponding dynamic threshold signal;
• and
• a detector, coupled to the multiplier and the short-term integrator, that asserts a timing signal based on a crossover between the short term moving average signal and the dynamic threshold signal.

A radio frequency (RF) transceiver configured for packet-based communication in which packets include pre-pended synchronization signals, comprising:

• a radio section configured to convert RF signals at a selected communication frequency received by an antenna into corresponding analog baseband signals;
• and
• a baseband processor, coupled to the radio, comprising:
• an analog to digital converter (ADC) that converts the analog baseband signals to digital signals;
• decimation filters, coupled to the ADC, that coverts the digital signals to digital samples at a selected sample rate;
• and
• timing estimation logic, coupled to the decimation filters, comprising:
• a correlator that compares the digital samples from the decimation filters with predetermined synchronization signals and that provides digital correlation samples indicative thereof;
• a short-term integrator, coupled to the phase corrector, that sums a first predetermined number of phase-corrected digital correlation samples and that provides a short term moving average signal;
• a long-term integrator, coupled to the phase corrector, that sums a second predetermined number of phase-corrected digital correlation samples and that provides a long term moving average signal, the second predetermined number greater than the first predetermined number;
• a multiplier, coupled to the long-term integrator, that multiplies the long term moving average signal by a predetermined scale factor and that provides a corresponding dynamic threshold signal;
• and
• a detector, coupled to the multiplier and the short-term integrator, that asserts a long sync timing signal based on a crossover between the short term moving average signal and the dynamic threshold signal.

A method of detecting synchronization signals of a packet transmitted in a multipath wireless medium, comprising:

• correlating an incoming signal with predetermined synchronization signals and providing a correlation signal indicative thereof;
• integrating the correlation signal over a predetermined short duration and providing a short-term moving average signal;
• integrating the correlation signal over a predetermined long duration and providing a long-term moving average signal;
• multiplying the long-term moving average signal by a scale factor and providing a corresponding dynamic threshold;
• and
• detecting a cross-over event between the short-term moving average signal and the dynamic threshold and asserting a timing signal indicative thereof.