Method and apparatus for de-spreading spread spectrum signals
AssigneeXilinx, Inc.
InventorKenneth D. Chapman
Life of this patent
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Abstract
A correlation circuit arrangement for de-spreading spread spectrum signals. In various embodiments, the correlation circuit arrangement includes an adder-subtractor and a shift register arrangement. The adder-subtractor adds an input sample value to or subtracts the sample value from an accumulated correlation value, responsive to an input PN code. The adder-subtractor is time-multiplexed between one or more PN code generators and correlation values are accumulated in the shift register arrangement. In another embodiment, transmission path delay can be analyzed by using the shift register arrangement to store correlation values that result from delaying the PN code across multiple chip periods.
Claims15
A multi-finger correlation circuit arrangement responsive to a stream of input sample values, comprising:
- a plurality of pseudo-random noise (PN) code generators, each configured to generate a respective PN code;
- a PN code selector coupled to the PN code generators;
- a shift register arrangement including a plurality of multi-bit locations for storing correlation values corresponding to each finger and having an output port at a last one of the locations;
- and
- an adder-subtractor having a first input port arranged to receive the stream of sample values, a second input port coupled to the PN code selector, and a third input port coupled to the output port of the shift register arrangement, wherein the adder-subtractor selects between add and subtract functions for application to values at the first and third input ports responsive to the PN code at the second input port.
A tracking correlation circuit arrangement for a de-spreader, the circuit arrangement being responsive to an input PN code and a stream of n input sample values per chip period, comprising:
- a first shift register arrangement including m * n multi-bit locations for storing correlation values and having an output port at a last one of the locations, wherein m is a number of chip periods over which a PN code bit is applied to input sample values;
- a second shift register including n bit storage elements, each bit storage element having an output port and a first one of the bit storage elements being arranged to receive the PN code;
- a selector coupled to the output ports of the bit storage elements of the second shift register and arranged to sequentially select bit values from the bit storage elements for each sample value in a chip period;
- and
- an adder-subtractor having a first input port coupled the output port of the first shift register arrangement, a second input port coupled to the output port of the second shift register, and a third input port arranged to receive the stream of sample values, wherein the adder-subtractor selects between add and subtract functions for application to values at the first and third input ports responsive to the signal at the second input port, the adder-subtractor further including a mask input port, and data at the third input port is masked responsive to a mask signal at the mask input port.
A correlation circuit arrangement, comprising:
- a pseudo-random noise (PN) code generator configured to generate a PN code;
- a storage element for storing a correlation value and including a plurality of input ports and output ports;
- a mask control circuit having a plurality of output ports and a plurality of input ports coupled to the output ports of the storage element, the mask control circuit configured to mask the result value at selected times;
- and
- a plurality of function generators configured as an adder-subtractor, the adder-subtractor having a first set of input ports coupled to the PN code generator for selecting between add and subtract functions, a second set of input ports for receiving bits of a sample input value, a third set of input ports coupled to output ports of the storage element, a fourth set of input ports coupled to the mask control circuit, and a set of output ports coupled to the input ports of the storage element, the adder-subtractor configured to selectively add or subtract values at the second and third sets of input ports responsive to the PN code at the first set of input ports.
Dependencies are inferred from the claim text.