# US 6,724,686 B2 · Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode

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- Number: US 6,724,686 B2
- Document ID: US6724686B2
- Status: Granted
- Kind: B2
- Application number: 10/339,288
- Filed: 2003-01-10
- Published: 2003-06-05
- Granted: 2004-04-20
- Earliest claimed: 1998-06-10
- Assignees: Renesas Technology Corp.
- Inventors: Tsukasa Ooishi; Masatoshi Ishikawa
- Web page: https://patentgrep.com/patent/US6724686B2

## CPC

- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns;
a control circuit controlling operation timing of said semiconductor memory device based on an external clock signal;
an interface circuit, controlled by said control circuit, receiving a control signal from the outside of said semiconductor memory device; and
a transmission timing change circuit changing transmission timing of said control signal to said memory cell array according to an operation mode.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein said transmission timing change circuit includes first and second transmission paths,
said first transmission path has a first switch circuit selectively transmitting said control signal from said interface circuit to said memory cell array according to said operation mode, and
said second transmission path has
a latch circuit holding the level of said control signal, and
a second switch circuit selectively transmitting said control signal from said latch circuit to said memory cell array according to said operation mode.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein said control signal is an address signal specifying selected column of said memory cell array.