Apparatus for pipe latch control circuit in synchronous memory device
AssigneeHynix Semiconductor Inc.
InventorKwan-Weon Kim
Life of this patent
Estimating the term…
Abstract
An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device. The apparatus includes a plurality of counting stages for counting in sequence in response to a data output buffer drive signal and a counting signal driver for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.
Claims16
An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device, comprising:
- a plurality of counting stages for counting in sequence in response to a data output buffer drive signal, said plurality of counting stages outputting a plurality of counting signals, respectively;
- and
- a counting signal drive means for generating the pipe output control signal by driving each counting signal outputted from the plurality of counting stages and controlled by the data output buffer drive signal, said counting signal drive means having a plurality of latch means, each of said latch means for receiving the data output buffer drive signal and a counting signal of said plurality of counting signals in order to reduce lost data access time.
An apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device, comprising:
- a plurality of counting stages for counting in sequence in response to a data output buffer drive signal;
- and
- a counting signal drive means for generating the pipe output control signal by driving each counting signal outputted from the plurality of counting stages and controlled by the data output buffer drive signal, said counting signal drive means including a plurality of latch means for latching each counting signal in response to the data output buffer drive signal, said latch means including a NAND latch having one input for the counting signal outputted from each counting stage and another input for the data output buffer drive signal.
Dependencies are inferred from the claim text.