# US 6,724,682 B2 · Nonvolatile semiconductor memory device having selective multiple-speed operation mode > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,724,682 B2 - Document ID: US6724682B2 - Status: Granted - Kind: B2 - Application number: 10/150,387 - Filed: 2002-05-17 - Published: 2002-12-05 - Granted: 2004-04-20 - Earliest claimed: 2001-06-01 - Assignees: Samsung Electronics Co., Ltd. - Inventors: June Lee; Heung-Soo Im; Sun-Mi Choi - Web page: https://patentgrep.com/patent/US6724682B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal. ## Claims ### Claim 1 A nonvolatile semiconductor memory device comprising: a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, each cell string formed with floating gate memory cell transistors having control gates respectively connected to a plurality of word lines, and wherein drain-source channels of the memory cell transistors are connected in series to each other between a string select transistor and a ground select transistor; a multiple-speed mode selector for generating a multiple-speed option signal; and an addressing circuit for selecting a different page size and block size of the memory cell array in response to a state of the multiple-speed option signal. ### Claim 2 (depends on 1) The memory device as claimed in claim 1, wherein the multiple-speed mode selector comprises a bonding pad that is selectively connected to power voltage. ### Claim 3 (depends on 1) The memory device as claimed in claim 1, wherein the multiple-speed mode selector is formed of a fuse or metal that can be cut. ### Claim 4 (depends on 1) The memory device as claimed in claim 1, wherein the addressing circuit comprises: a row decoder for decoding a mat select address signal out of input row address signals in response to the multiple-speed option signal, and receiving the decoded mat select address signals and input row address signals to thereby generate row decoding signals for selecting, during a multiple-speed mode operation, a page size more than two times a page size of a default mode operation; a column address counter for generating column address signals that allow an antilogarithm counting operation to perform differently in response to a state of the multiple-speed signal; and a column decoder for decoding column address signals input from the column address counter to thereby generate column decoding signals for selecting during the multiple-speed mode operation a block size more than two times the block size of the default mode operation. ### Claim 5 (depends on 4) The memory device as claimed in claim 4, wherein the row decoder comprises: a mat select signal decoder for decoding the multiple-speed option signal and the mat select address signal to thereby generate decoding mat select address signals; a P pre-decoder for pre-decoding first group addresses out of the input row address signals; a Q pre-decoder for pre-decoding second group addresses that are at a higher level than the first group addresses out of the input row address signals; and R1 and R2 pre-decoders for pre-decoding third group addresses that are at a higher level than the second group addresses out of the input row address signals in response to the decoding mat select address signals. ### Claim 6 (depends on 4) The memory device as claimed in claim 4, wherein the column address counter is connected to a column address counter controller through a plurality of D type flip-flops and a signal selector, and operates as a 10-antilogarithm counter or 11-antilogarithm counter in response to a state of the multiple-speed option signal. ### Claim 7 (depends on 1) The memory device as claimed in claim 1, further comprising an output circuit for outputting a device identification signal in response to a state of the multi-speed option signal. ### Claim 8 A nonvolatile semiconductor memory device comprising: a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, each cell string formed with floating gate memory cell transistors having control gates respectively connected to a plurality of word lines, and wherein drain-source channels of the memory cell transistors are connected in series to each other between a string select transistor and a ground select transistor; a multiple-speed mode option part for generating a multiple-speed option signal; a row decoder for decoding a mat select address signal out of input row address signals in response to the multiple-speed option signal, and receiving the decoded mat select address signals and input row address signals to thereby generate row decoding signals for selecting during a multiple-speed mode operation a page size more than two times the page size of a default mode operation; a column address counter for generating column address signals that allow an antilogarithm counting operation to perform differently in response to a state of the multiple-speed signal; and a column decoder for decoding column address signals output from the column address counter to thereby generate column decoding signals for selecting during the multiple-speed mode operation a block size more than two times the block size of the default mode operation; and a page buffer controller for controlling operations of page buffers corresponding to the page and block sizes in response to a state of the multiple-speed signal. ### Claim 9 (depends on 8) The memory device as claimed in claim 8, wherein the column address decoder performs a decoding operation by adding and subtracting column addresses in response to a state of the multiple-speed option signal. ### Claim 10 (depends on 8) The memory device as claimed in claim 8, wherein the row address decoder performs a decoding operation by adding and subtracting row addresses in response to a state of the multiple-speed option signal. ### Claim 11 A method of driving a nonvolatile semiconductor memory device comprising a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings that are formed of floating gate memory cell transistors having control gates respectively connected to a plurality of word lines, and having drain-source channels that are series connected to each other between a string select transistor and a ground select transistor, the method comprising: forming a multiple-speed option part for generating a multiple-speed option signal according to a device option in the device; and performing addressing to enlarge page and block sizes of the memory cell array by more than two times in response to a state of the multiple-speed option signal, enabling reading, writing and erasing to be performed at a multiple-speed mode operation. ### Claim 12 A semiconductor memory device having flash memory cells, comprising an address counter, a column decoder, and a row decoder that are option-controlled so that block and page sizes predetermined at a hardware design can be changed according to a device option. ### Claim 13 A non-volatile memory device, comprising: a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings; a multiple-speed mode selector for generating a multiple-speed option signal, the multiple-speed option signal having at least a first state and a second state; and an address circuit structured to generate a first page size and block size for the memory cell array in response to the first state of the multiple-speed option signal, and structured to generate a second page size and block size for the memory cell array in response to the second state of the multiple-speed option signal. ### Claim 14 (depends on 13) The memory device according to claim 13, wherein the multiple-speed mode selector comprises a bonding pad that is adapted to be coupled to a power voltage. ### Claim 15 (depends on 13) The memory device according to claim 13, further comprising an output circuit for outputting a device identification signal in response to a state of the multi-speed option signal. ### Claim 16 A method for operating a memory device, comprising: generating a multiple-speed signal; sensing a state of the multiple-speed signal at an addressing circuit coupled to a memory array in the memory device; and changing page and block sizes of the memory cell array in response to the state of the multiple-speed option signal. ### Claim 17 (depends on 16) The method according to claim 16, wherein generating a multiple-speed signal comprises coupling a multiple-speed signal generating circuit to a power voltage. ### Claim 18 (depends on 16) The method according to claim 16 wherein sensing a state of the multiple-speed signal at an addressing circuit comprises sensing a state of the multiple-speed signal at a row pre-decoding circuit an at a column pre-decoding circuit. ### Claim 19 (depends on 16) The method according to claim 16, wherein changing page and block sizes of the memory cell array comprises operating a column address counter as a 10-antilogarthim counter when it senses a first state of the multiple-speed signal, and operating a column address counter as an 11-antilogarithm counter when it senses a second state of the multiple-speed signal. ### Claim 20 (depends on 16) The method according to claim 16, further comprising outputting a device identification signal in response to a state of the multi-speed option signal.