Semiconductor memory device allowing high density structure or high performance

A semiconductor memory device comprising:

• banks of n (n is a natural number) in number each including a plurality of memory cells;
• predecoders of m (m is a natural number satisfying (m<n)) in number for producing a select signal for selecting each of said n banks;
• a pump circuit for boosting a power supply voltage to a word line activation voltage;
• and
• a power supply interconnection for supplying said word line activation voltage to each of said plurality of banks, wherein
• each of said m predecoders outputs said produced select signal to the banks of k (k is a natural number satisfying (n=k×m)) in number among said n banks;
• each of said n banks includes:
• a plurality of memory cells arranged in rows and columns,
• a plurality of word lines arranged in a row direction,
• a plurality of bit line pairs arranged in a column direction, and
• a word line driver for activating, with said word line activation voltage, the word line among said plurality of word lines designated by an address;
• said pump circuit includes:
• a pump capacitor for boosting said power supply voltage to said word line activation voltage, and
• an interconnection for supplying said word line activation voltage formed of a voltage between the opposite ends of said pump capacitor to said power supply interconnection;
• and
• a longitudinal direction of said pump capacitor is the same as the direction of said interconnection.